硬件编程语言 vhdl

---

title: 硬件编程语言的部分程序实现

tags: 硬件编程语言

---

编程语言

7人投票表决器

1、利用全加器实现

library ieee;

use ieee.std_logic_1164.all;

entity vote7 is port(

    a,b,c,d,e,f,g:in std_logic;

pass:out std_logic);

architecture one of vote7 is

  component f_adder port(

  ain,bin,cin:in std_logic;

  sum,cout:out std_logic);

  end component;

    signal b1,c1,a2,b2,c2:std_logic;

begin

  u1:f_adder port map(ain=>a,bin=>b1,cin=>c1,cout=>a2,sum=>open);

  u2 : f_adder port map(ain=>a2,bin=>b2,cin=>c2,cout=>pass,sum=>open);

    u3 : f_adder port map(ain=>b,bin=>c,cin=>d,cout=>b2,sum=>b1);

    u4 : f_adder port map(ain=>e,bin=>f,cin=>g,cout=>c2,sum=>c1);

end one;

2、直接实现

LIBRARY ieee;

USE ieee.Std_logic_1164.ALL;

USE ieee.Std_logic_unsigned.ALL;  --运算操作符

ENTITY vote7 IS

PORT(

datain : IN Std_logic_vector(6 DOWNTO 0);

termcnt : OUT Std_logic);

END vote7;

ARCHITECTURE v1 OF vote7 IS

BEGIN

main_proc : PROCESS(datain)

variable tsum:integer range 0 to 7;

BEGIN

tsum := 0;

FOR i IN datain'Range LOOP

IF datain(i) = '1' THEN

tsum := tsum+1;

END IF;

END LOOP;

if tsum>=4 then

    termcnt<='1';

else

    termcnt<='0';

end if;

END PROCESS;

END v1;

4选1数据选择器

USE ieee.std_logic_1164.all

ENTITY mux4 IS

  PORT (i0,i1,i2,i3,a,b :IN STD_LOGIC);

        q :OUT STD_LOGIC);

END mux4

ARCHOITECTUR OF mux4 IS

  SIGNAL sel :INTEGER;

BEGIN

  WITH sel SELECT

  q <=  i0  WHEN 0,

    i1  WHEN 1,

    i2  WHEN 2,

    i3  WHEN 3,

    'X' WHEN OTHERS;

  sel <= 0 WHEN a = '0' AND b = '0' ELSE

    1 WHEN a = '1' AND b = '0' ELSE

    2 WHEN a = '0' AND b = '1' ELSE

    3 WHEN a = '1' AND b = '1' ELSE

    4;

END;