HDLbits Count clock 练习

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    reg [3:0] ss_0,ss_1,mm_0,mm_1,hh_0,hh_1;//ss_0,ss_1分别是秒的两位计数
    reg pm_temp;
    
    assign ss={ss_1,ss_0};
    assign mm={mm_1,mm_0};
    assign hh={hh_1,hh_0};
    assign pm = pm_temp;
    
    //秒钟的控制
    always @(posedge clk) begin
        if(reset) 
            ss_0 <= 4'h0;
        else if(ena && ss_0==4'h9) //到10进1
            ss_0 <= 0;
        else if(ena && ss_0!=4'h9) //未到10继续累加
            ss_0 <= ss_0 + 4'h1; 
        else
            ss_0 <= ss_0;
    	end 
    always @(posedge clk) begin
        if(reset) 
            ss_1 <= 4'h0;
        else if(ena && ss_0==4'h9 && ss_1==5) //到59进位
            ss_1 <= 0;
        else if(ena && ss_0==4'h9 && ss_1!=5)
            ss_1 <= ss_1 + 4'h1; 
        else
            ss_1 <= ss_1;
    	end
    //分钟的控制
    always @(posedge clk) begin
        if(reset) 
            mm_0 <= 4'h0;
        else if(ena && mm_0==4'h9 && ss_1==4'h5 && ss_0==4'h9)//到9'59''时进位
            mm_0 <= 0;
        else if(ena && mm_0!=4'h9 && ss_1==4'h5 && ss_0==4'h9)
            mm_0 <= mm_0 + 4'h1; 
        else
            mm_0 <= mm_0;
    	end 
    always @(posedge clk) begin
        if(reset) 
            mm_1 <= 4'h0;
        else if(ena && mm_1==4'h5 && mm_0==4'h9 && ss_1==4'h5 && ss_0==4'h9)//到59'59''进位
            mm_1 <= 0;
        else if(ena && mm_1!=4'h5 && mm_0==4'h9 && ss_1==4'h5 && ss_0==4'h9)
            mm_1 <= mm_1 + 4'h1; 
        else
            mm_1 <= mm_1;
    	end
    //时钟的控制
    always @(posedge clk) begin
        if(reset) 
            hh_0 <= 4'h2;
        else if(ena && hh_1==4'h0 && hh_0==9 && mm_1==4'h5 && mm_0==9 && ss_1==4'h5 && ss_0==4'h9)//到9.59'59''进位
            hh_0 <= 4'h0;
        else if(ena && hh_1==4'h1 && hh_0==4'h2 && mm_1==4'h5 && mm_0==9 && ss_1==4'h5 && ss_0==4'h9)//到12.59'59''进位
            hh_0 <= 4'h1;
        else if(ena && hh_1==4'h0 && hh_0!=9 && mm_1==4'h5 && mm_0==9 && ss_1==4'h5 && ss_0==4'h9)
            hh_0 <= hh_0 + 4'h1; 
        else if(ena && hh_1==4'h1 && hh_0!=4'h2 && mm_1==4'h5 && mm_0==9 && ss_1==4'h5 && ss_0==4'h9)
            hh_0 <= hh_0 + 4'h1; 
        else
            hh_0 <= hh_0;
    	end
    always @(posedge clk) begin
        if(reset) 
            hh_1 <= 4'h1;
        else if(ena && hh_1==4'h1 && hh_0==4'h2 && mm_1==4'h5 && mm_0==4'h9 && ss_1==4'h5 && ss_0==4'h9)
            hh_1 <= 4'h0;
        else if(ena && hh_1!=4'h1 && hh_0==4'h9 && mm_1==4'h5 && mm_0==4'h9 && ss_1==4'h5 && ss_0==4'h9)
            hh_1 <=hh_1 + 4'h1; 
        else
            hh_1 <= hh_1;
    	end
    //判断上午下午，每到11:59:59翻转一次。
    always @(posedge clk) begin
        if (reset)
            pm_temp <= 0;
        if(ena && hh_1==4'h1 && hh_0==4'h1 && mm_1==4'h5 && mm_0==9 && ss_1==4'h5 && ss_0==4'h9)
            pm_temp <= ~pm_temp; 
    	else
            pm_temp <= pm_temp;  end
endmodule