Verilog HDL串口发送程序

module myuart_trans(

    input clk,   

    input rst,

    input TransEn,           //transmit able

    input[7:0] DataToTrans,  //Data prepared for transmitting

    output reg BufFull,      //Data buffer is full

    output reg tx,           //serial data out

    output reg gnd=1'b0

);



//对50MHz晶振进行分频，3.125MHz

reg[7:0] count;

reg clk16x;

always@(posedge clk or posedge rst)

    if(rst) 

        begin

            count<=8'd0;

            clk16x=1'b0;

        end

    else if(count>=8'd125)

        begin

            count<=1'b0;

            clk16x=~clk16x; 

        end

    else count<=count+1'b1;

    

//capture the falling edge of TransEn

reg TransEn_r;

wire pos_tri;

always@(posedge clk16x or posedge rst)

    if(rst) TransEn_r <= 1'b0;

    else TransEn_r <= TransEn;

assign pos_tri = TransEn_r & ~TransEn;



// when the falling edge of TransEn,load the Data to buffer

reg[7:0] ShiftReg;

always@(negedge pos_tri or posedge rst)

    if(rst) ShiftReg <= 8'b0;

    else ShiftReg <= DataToTrans;

    

//counter control

reg cnt_en;

always@(posedge clk16x or posedge rst)

    if(rst)

        begin

            cnt_en <= 1'b0;

            BufFull <= 1'b0;

        end

    else if(pos_tri==1'b1)

        begin

            cnt_en <= 1'b1;

            BufFull <= 1'b1;

        end

    else if(cnt==168)

        begin

            cnt_en <= 1'b0;

            BufFull <= 1'b0;

        end

        

//counter module

reg[7:0] cnt;

always@(posedge clk16x or posedge rst)

    if(rst) cnt <= 8'd0;

    else if(cnt_en) cnt <= cnt+1'b1;

    else cnt <= 8'd0;

    

//transmit module

always@(posedge clk16x or posedge rst)

    if(rst) tx <= 1'b1;

    else if(cnt_en)

        case(cnt)

            8'd8: tx <= 1'b0;

            8'd24: tx <= ShiftReg[0];

            8'd40: tx <= ShiftReg[1];

            8'd56: tx <= ShiftReg[2];

            8'd72: tx <= ShiftReg[3];

            8'd88: tx <= ShiftReg[4];

            8'd104: tx <= ShiftReg[5];

            8'd120: tx <= ShiftReg[6];

            8'd136: tx <= ShiftReg[7];

            8'd152: tx <= 1'b1;

        endcase

    else tx <= 1'b1;

    

endmodule