VHDL同步清零、并行输出的8位逻辑左移移位寄存器

要求设计一个具有同步清零、并行输出的8位逻辑左移移位寄存器，（高位为左，低位为右，）其引脚名称和逻辑功能如下表所示。

library ieee;
use ieee.std_logic_1164.all;

entity L_shifter8 is
	port	( clk,clr,si  : in 	std_logic;
		  d	       : buffer    std_logic_vector(7 downto 0);
		  so	       : out         std_logic  );
end entity L_shifter8;
architecture rtl of L_shifter8 is
begin
	process (clk)
	begin	
		if (clk'event) and (clk='1') then
			if clr = '0' then
				d <= "00000000"; so <= '0';
			else
				d(7 downto 1) <= d(6 downto 0); 
				d(0) <= si;
				so <= d(6);
			end if;
		end if;
	end process;
end rtl;