hdlbits_ece241_2013_q8

https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q8

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
	
    
    parameter idle=0,S1=1,S2=2;
    
    reg [1:0]state,next;
    
    always @(*)
        begin
            case(state)
                idle: next=x?S1:idle;
                S1: next = x?S1:S2;
                S2: next = x? S1:idle;
            endcase
        end
    
    always @(posedge clk or negedge aresetn)
        begin
            if (!aresetn)
                state <= idle;
            else
                state <= next;
        end
    assign z =(state == S2) && (x==1'b1);
endmodule