串并转换verilog

串并转换verilog

verilog如下

//串并转换
//串转并
module serial2parallel(
	input clk,
	input rst_n,
	input datain,
	input shift_en,
	input load,
	output reg [15:0] dataout);
	
reg [15:0] shiftr;
//串转并
always@(posedge clk)
	if(!rst_n)
		shiftr<=0;
	else if(shift_en)
	shiftr<={shiftr[14:0],datain};

// load
always@(posedge clk)
	if(!rst_n)
		dataout<=0;
	else if(load)
	dataout<=shiftr;
//assign dataout= load ? shiftr : 0;
//两种dataout时序不一样	
endmodule

//并转串
module parallel2serial(
	input clk,
	input rst_n,
	input [15:0] datain,
	input shift_en,
	input load,
	output dataout);
	
reg [15:0] shiftr;
//shift
always@(posedge clk)
	if(!rst_n)
		shiftr<=0;
	else if(load)
	shiftr<=datain;
	else if(shift_en)
	shiftr<=shiftr<<1;
	
assign dataout=shiftr[15];

endmodule

tb(sv)如下

module tb(  );
logic clk, rst_n, datain1, dataout2;
logic shift_en1, shift_en2, load1, load2;
logic [15:0] datain2, dataout1;
//实例化，将串接口相连
serial2parallel serial2parallel(clk, rst_n, dataout2,shift_en1, load1, dataout1);
parallel2serial parallel2serial (clk, rst_n, datain2, shift_en2, load2, dataout2);

initial begin clk=0; forever #5 clk=~clk; end
initial begin rst_n=0; #30 rst_n=1; end

initial begin
load1=0; load2=0;
#40 load2=1; shift_en1=1; shift_en2=1;  datain2=16'h67;
#10 load2=0; 
#150 
load1=1;
end

endmodule