关于同步fifo空满信号的讨论

今天突然想手写一下同步fifo的verilog代码，但是突然想不通fifo的空满信号应该在什么时候拉高了。

例如：fifo的深度为4，假设从第一个周期wr_en持续拉高，那么是在第4个周期full拉高，还是第5个周期full拉高？
因为一般往fifo里写数据都是这样写：
always @(posedge clk)begin
if(rst)begin
wr_en <= 1’b0;
end
else if(~full)begin
wr_en <= 1’b1;
end
else begin
wr_en <= 1’b0;
end
end
本人感觉应该是wr_en持续4个周期的高电平以后，full在第5个周期拉高，但是第5个周期的wr_en还是高的，也就是会出现空写的问题；如果
full是在第4个周期拉高的，那么就会出现实际上没有写满的问题。所以有点搞不懂了，以下贴出写的同步fifo的verilog代码和仿真结果，请大神指点

`timescale 1ns / 1ps
module Syn_Fifo #(
		parameter DEPTH = 10,
	parameter WIDTH = 16
)(
	input clk,
	input rst,
	input [WIDTH-1:0] din,
	input wr_en,
	input rd_en,
	output reg [WIDTH-1:0] dout,
	output reg full,
	output reg empty,
	output reg valid
);

reg [clogb2(DEPTH-1)-1:0] head, tail;
reg [clogb2(DEPTH)-1:0] count;
reg [WIDTH-1:0] fifomem [0:DEPTH-1];

always @(posedge clk)begin
	if(rst == 1'b1)begin
		dout <= 'b0;
	end
	else if(rd_en == 1'b1 && empty == 1'b0)begin
		dout <= fifomem[tail];
	end
	else begin
		dout <= 'b0;
	end
end

always @(posedge clk)begin
	if(rst == 1'b1)begin
		valid <= 'b0;
	end
	else if(rd_en == 1'b1 && empty == 1'b0)begin
		valid <= 1'b1;
	end
	else begin
		valid <= 'b0;
	end
end

always @(posedge clk)begin
	if(rst == 1'b0 && wr_en == 1'b1 && full == 1'b0)begin
		fifomem[head] <= din;
	end
end

always @(posedge clk)begin
	if(rst == 1'b1)begin
		head <= 'b0;
	end
	else if(wr_en == 1'b1 && full == 1'b0)begin
		if(head == DEPTH-1)begin
			head <= 'd0;
		end
		else begin
			head <= head + 'd1;
		end
	end
	else begin
		head <= head;
	end
end

always @(posedge clk)begin
	if(rst == 1'b1)begin
		tail <= 'b0;
	end
	else if(rd_en == 1'b1 && empty == 1'b0)begin
		if(tail == DEPTH-1)begin
			tail <= 'd0;
		end
		else begin
			tail <= tail + 'd1;
		end
	end
	else begin
		tail <= tail;
	end
end

always @(posedge clk)begin
	if(rst == 1'b1)begin
		count <= 'b0;
	end
	else begin
		case({wr_en,rd_en})
			2'b00:count <= count;
			2'b01:if(count != 'd0)
					count <= count - 1'd1;
				  else
					count <= count;
			2'b10:if(count != DEPTH)
					count <= count + 'd1;
			2'b11:count <= count;
			default:count <= count;
		endcase
	end
end

always @(count)begin
	if(count == 'd0)begin
		empty = 1'b1;
	end
	else begin
		empty = 1'b0;
	end
end

always @(count)begin
	if(count == DEPTH)begin
		full = 1'b1;
	end
	else begin
		full = 1'b0;
	end	
end

function integer clogb2(input integer DEPTH);
	begin
		for(clogb2=0; DEPTH>0; clogb2 = clogb2 + 1)
			DEPTH = DEPTH >> 1;
	end
endfunction
endmodule