SystemVerilog Inline Constraints（SystemVerilog内联约束）

考虑到一个类已经有写得很好的约束，因此需要根据用户决定的一组不同约束来随机化该类变量。 通过使用with构造，用户可以在调用randomize（）方法的位置声明内联约束。 这些附加约束将与求解器将考虑的对象原始约束一起考虑。

Example

class Item;
  rand bit [7:0] id;
 
  constraint c_id {
      id < 25; }
 
endclass
 
module tb;
 
  initial begin
    Item itm = new ();
    itm.randomize() with {
      id == 10; };     // In-line constraint using with construct
    $display ("Item Id = %0d", itm.id);
  end
endmodule

Simulation Log
run -all;
# KERNEL: Item Id = 10
# KERNEL: Simulation has finished. There are no more test vectors to simulate.

请注意，此处已应用内联约束，因此随机ID为10。
如果原始约束c_id固定为25，如下所示，并且我们提供了冲突的内联值，则随机化将失败。

class Item;
  rand bit [7:0] id;
 
  constraint c_id {
      id == 25; }
endclass
 
module tb;
  initial begin
    Item itm = new ();
    if (! itm.randomize() with {
      id < 10; })
      $display ("Randomization failed");
    $display ("Item Id = %0d", itm.id);
  end
endmodule
 
Simulation Log
ncsim> run
    if (! itm.randomize() with {
      id < 10; })
                      |
ncsim: *W,SVRNDF (./testbench.sv,10|22): The randomize method call failed.
Observed simulation time : 0 FS + 0
ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints:

  constraint c_id {
      id == 25; }; (./testbench.sv,4)
    if (! itm.randomize() with {
      id < 10; }) (./testbench.sv,10)
ncsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints:

rand variables:
       id [./testbench.sv, 2]

Randomization failed
Item Id = 0
ncsim: *W,RNQUIE: Simulation is complete.

参考文献：
【1】https://www.chipverify.com/systemverilog/systemverilog-inline-constraints