Verilog时钟n分频

n分频模块实现如下：

module ndivision(clk_in, clk_out, reset_low);
  input clk_in,reset_low;
  output reg clk_out;
  reg [4:0] cnt;
  parameter CNT_NUM = 20;
  parameter CNT_HIGH = 10;
  
  initial
  begin
    cnt = 0;
    clk_out = 0;
  end
  
  always @(posedge clk_in or negedge reset_low)
  begin
    cnt = cnt + 1;
    if(cnt <= CNT_HIGH)
      begin
        clk_out = 1;
      end
    else
      begin
        clk_out = 0;
        if(cnt == CNT_NUM)
          begin
            cnt = 0;
          end
      end
      
    if(!reset_low)
      begin
        clk_out = 0;
        cnt = 0;
      end
  end
endmodule

测试代码如下：

`timescale 1us/100ns
`include "ndivision.v"

module ndivision_test;
  wire clk_out;
  reg clk_in,reset;
  
  always
  begin
    #0.1 clk_in = ~clk_in;
  end
  
  initial
  begin
    clk_in = 0;
    reset = 1;
    
    #2.2 reset = 0;
    #0.2 reset = 1;
    #1000 $stop;
  end
  
  ndivision #(20,15) u1ndivision(.clk_in(clk_in),.clk_out(clk_out),.reset_low(reset));
endmodule