MESI - Intel 奔腾系列 CPU的缓存一致性协议

MESI

MESI是啥？

==> MESI是一种缓存一致性协议

为什么要有MESI？

==> 为了协调多个CPU核心上的缓存，使数据保持一致

首先，由于CPU和内存的速度不匹配，所以有了CPU高速缓存，现代CPU的缓存一般分为3级，L1，L2，L3，通常来讲，一个多核处理器上，每个CPU核心都有自己的L1和L2 Cache，L3 Cache则是被所有核心共享的。CPU读取某一数据时，会先从缓存中读，若缓存read miss，则将数据从主存加载到缓存。缓存中的一个数据单位称为一个缓存行（cache line），通常是64字节，从主存中加载数据到缓存，不是一次加载一个字节，而是一次加载一个缓存行。

MESI用来保证多个cache之间的数据一致性

MESI的工作原理

MESI是一种基于失效，并支持回写（write-back）的缓存一致性协议。由于该协议在伊利诺伊大学被发明，所以也叫伊利诺伊协议。

MESI protocol is an Invalidate-based cache coherence protocol, and is one of the most common protocols which support write-back caches.It is also known as Illinois protocol

MESI这4个首字母缩写分别代表了一个缓存行（cache line）的4种状态

1. Modified

   该cache line只存在于当前cache，而不存在于其他cache，并且该cache line的数据与主存中的数据不一致，是脏数据（dirty）

2. Exclusive

   该cache line只存在于当前cache，而不存在于其他cache，并且该cache line的数据与主存中的数据一致，是clean的

3. Shared

   该cache line存在于多个cache中，并且该cache line 的数据与主存中的数据一致

4. Invalid

   该cache line 失效

MESI协议其实就是一个有限状态机（Finite State Machine）的模型，在这个FSM中，定义了4种状态，以及2类导致状态发生转换的激励（stimuli）。简单的说，MESI就是4种状态，加2种激励。

每个cache需要接收来自其所属的cpu的读写指令，还要监听总线上发生的事件（bus snooping）。

2种stimuli如下

• 第一种stimuli是cpu端的，某个cpu核对其cache发出的操作，包括了读和写

  1. PrRd

     The processor request to read a cache block

     处理器发起了对其cache的读请求

  2. PrWr :

     The processor request to write a cache block

     处理器发起了对其cache的写请求

• 第二种stimuli是总线端的，由cache controller监听到的总线上的事件

  1. BusRd

     Snooped request that indicates there is a read request to a cache block made by another processor

     某个cache嗅探到总线bus上有一个其他处理器发出的读请求

  2. BusRdX

     Snooped request that indicates there is a write request to a cache block made by another processor which doesn’t have the block

     某个cache嗅探到总线bus上有一个其他处理器发出的写请求，并且该处理器的cache本身不含有这个数据

  3. BusUpgr

     Snooped request that indicates there is a write request to a cache block made by another processor but that processor already has that cache block resides in its cache

     某个cache嗅探到总线bus上有一个其他处理器发出的写请求，并且该处理器的cache本身包含了这个数据

  4. Flush

     Snooped request that indicates that an entire cache block is written back to the main memory by another processor

     某个cache嗅探到其他处理器将某个cache block写回到了主存

  5. FlushOpt

     Snooped request that indicates that an entire cache block is posted on the bus in order to supply it to another processor (Cache to cache transfer)

     某个cache嗅探到有一个cache block在总线上传递

  The State transitions and the response at a particular state with respect to different inputs are shown as follow

Initial State	Operation	Response
Invalid(I)	PrRd	Issue BusRd to the busother Caches see BusRd and check if they have a non-invalid copy, inform sending cacheState transition to (S)Shared, if other Caches have non-invalid copy.State transition to (E)Exclusive, if none (must ensure all others have reported).If other Caches have copy, one of them sends value, else fetch from Main Memory
	PrWr	Issue BusRdX signal on the busState transition to (M)Modified in the requestor Cache.If other Caches have copy, they send value, otherwise fetch from Main MemoryIf other Caches have copy, they see BusRdX signal and Invalidate their copies.Write into Cache block modifies the value.
Exclusive(E)	PrRd	No bus transactions generatedState remains the same.Read to the block is a Cache Hit
	PrWr	No bus transaction generatedState transition from Exclusive to (M)ModifiedWrite to the block is a Cache Hit
Shared(S)	PrRd	No bus transactions generatedState remains the same.Read to the block is a Cache Hit.
	PrWr	Issues BusUpgr signal on the bus.State transition to (M)Modified.other Caches see BusUpgr and mark their copies of the block as (I)Invalid.
Modified(M)	PrRd	No bus transactions generatedState remains the same.Read to the block is a Cache hit
	PrWr	No bus transactions generatedState remains the same.Write to the block is a Cache hit.

Initial State	Operation	Response
Invalid(I)	BusRd	No State change. Signal Ignored.
	BusRdX/BusUpgr	No State change. Signal Ignored
Exclusive(E)	BusRd	Transition to Shared (Since it implies a read taking place in other cache).Put FlushOpt on bus together with contents of block.
	BusRdX	Transition to Invalid.Put FlushOpt on Bus, together with the data from now-invalidated block.
Shared(S)	BusRd	No State change (other cache performed read on this block, so still shared).May put FlushOpt on bus together with contents of block (design choice, which cache with Shared state does this).
	BusRdX	Transition to Invalid (cache that sent BusRdX becomes Modified)May put FlushOpt on bus together with contents of block (design choice, which cache with Shared state does this)
Modified(M)	BusRd	Transition to **(S)Shared.**Put FlushOpt on Bus with data. Received by sender of BusRd and Memory Controller, which writes to Main memory.
	BusRdX	Transition to (I)Invalid.Put FlushOpt on Bus with data. Received by sender of BusRdx and Memory Controller, which writes to Main memory.

参考链接：
https://en.wikipedia.org/wiki/MESI_protocol