【SystemVerilog】define的一种用法

今天有用到define的一种用法，在这share一下，直接上例子~~

 

module top ;

  `define A_SRAM_RW(dst_cc_num,src_cc_num)\
     if(strm_sel[``dst_cc_num``] == 1'b1)begin\
       force top.my_dut.strm_in``dst_cc_num``_en = top.my_dut.strm_in``src_cc_num``_en;\
     end

  initial begin
    `A_SRAM_RW(1,0)
    `A_SRAM_RW(2,0)
  end

endmodule

result:

module top;
  initial begin
     if(strm_sel[1] == 1'b1)begin
       force top.my_dut.strm_in1_en = top.my_dut.strm_in0_en;
     end
     if(strm_sel[2] == 1'b1)begin
       force top.my_dut.strm_in2_en = top.my_dut.strm_in0_en;
     end
  end
endmodule

---

上栗中，dst_cc_num和src_cc_num是要传进来的参数，引用传进来的参数时要在参数前和后加``，不接收传进来的变量，比如

generate 
  for(genvar jj=1;jj<`CC_NUM；jj++)begin
    `A_SRAM_RW(jj,0)
  end
endgenerate

上面这种写法是不行的，相当于只是把jj传进了define中，并不会把jj所代表的值传进去。

From reading these it might be apparent that define macro can be used for adding a postfix to the variable, but not prefix. I was thinking the same after reading the description (they don't have a single example of adding prefix to the variable via `define. Confused ?? Let me explain by giving a concrete example

view sourceprint?
// Example macro for a coverage class
// Aim : want to get ABC_cp : coverpoint ABC {bins b = {1}; }
// by calling `COV(ABC)
`define COV(__name) __name``_cp : coverpoint __name {bins b = {1}; }

// Next
//     What to do if I want cp_ABC in place of ABC_cp as for the above example
//     NOTE : I can't use cp_``__name as cp_ is not an input to the macro
// Solution

//     Use nested macros

`define PREFIX(__prefix, __name) __prefix``__name

`define COV2(__name) `PREFIX(cp_,__name) : coverpoint __name {bins b = {1}; }

`" 和 `\ 是对"和\进行转义

`define data_to_reg(ARG1) \
   $display("Reg name: reg_%0s,value: %0h",`"ARG1`",reg_``ARG1);


`data_to_reg(a)

等效于
$display("Reg name: reg_a,value: %0h","a",reg_a);

`define data_to_reg(ARG1) \
   $display(`"Reg name: `\`"ARG1`\`",value: %0h`",ARG1);


`data_to_reg(reg_a)

等效于
$display("Reg name: \"reg_a\",value: %0h",reg_a);