Verilog--边沿检测

//边沿检测电路

//方法一：打一拍后，看前后是否相反
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		a_ff0 <= 1'b0;
	end
	else begin
		a_ff0 <= a;
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		pedge <= 1'b0;
		nedge <= 1'b0;
	end
	else if(a==1'b1&&a_ff0==1'b0) begin		
		pedge <= 1'b1;
	end
	else if(a==1'b0&&a_ff0==1'b1) begin
		nedge <= 1'b1;
	end
	else begin
		pedge <= 1'b0;
		nedge <= 1'b0;
	end
end

//方法一：打两拍后，看前后是否相反
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			{buf2,buf1} <= 2'b0;
		end
		else begin
			{buf2,buf1} <= {buf1,wr_en};
		end
	end
	assign nedge = ({buf2,buf1}==2'b10)?1'b1:1'b0;
	assign pedge = ({buf2,buf1}==2'b01)?1'b0:1'b1;