core-v-verif系列之cv32e40p UVM环境介绍＜11＞

UVM环境介绍
HEAD commitID： 1f968ef

1. regress/cv32e40p_full_covg_no_pulp.yaml

# YAML file to specify a regression testlist
# Note that the COREV=YES is set for all tests in this regression.
# This means you need to have a toolchain at COREV_SW_TOOLCHAIN (see Common.mk)
---
# Header
name: cv32_full_covg_no_pulp
description: Full regression (all tests) for CV32E40P with step-and-compare against RM"

# List of builds
builds:
  clean_fw:
    cmd: make clean-bsp clean_test_programs
    dir: cv32e40p/sim/uvmt
  corev-dv:
    cmd: make clean_riscv-dv comp_corev-dv
    dir: cv32e40p/sim/uvmt
    cov: 0
  uvmt_cv32e40p:
    cmd: make comp
    dir: cv32e40p/sim/uvmt

# List of tests
tests:
  hello-world:
    build: uvmt_cv32e40p
    description: uvm_hello_world_test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=hello-world

  csr_instructions:
    build: uvmt_cv32e40p
    description: CSR instruction test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=csr_instructions

  generic_exception_test:
    build: uvmt_cv32e40p
    description: Generic exception test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=generic_exception_test

  illegal_instr_test:
    build: uvmt_cv32e40p
    description: Illegal instruction test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=illegal_instr_test

  branch_zero:
    build: uvmt_cv32e40p
    description: Branch test with zero offsets
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=branch_zero

  cv32e40p_csr_access_test:
    build: uvmt_cv32e40p
    description: CSR Access Mode Test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=cv32e40p_csr_access_test

  cv32e40p_readonly_csr_access_test:
    build: uvmt_cv32e40p
    description: CSR Read-only Access Mode Test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=cv32e40p_readonly_csr_access_test

  requested_csr_por:
    build: uvmt_cv32e40p
    description: CSR PoR test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=requested_csr_por

  modeled_csr_por:
    build: uvmt_cv32e40p
    description: Modeled CSR PoR test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=modeled_csr_por

  csr_instr_asm:
    build: uvmt_cv32e40p
    description: CSR instruction assembly test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=csr_instr_asm

  perf_counters_instructions:
    build: uvmt_cv32e40p
    description: Performance counter test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=perf_counters_instructions

  mhpmcounter29_csr_access_test_1:
    build: uvmt_cv32e40p
    description: Hardware performance counter full access coverage test 1
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_1

#  mhpmcounter29_csr_access_test_2:
#    build: uvmt_cv32e40p
#    description: Hardware performance counter full access coverage test 2
#    dir: cv32e40p/sim/uvmt
#    cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_2
#    iss: 0

  hpmcounter_basic_test:
    build: uvmt_cv32e40p
    description: Hardware performance counter basic test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=hpmcounter_basic_test

  hpmcounter_hazard_test:
    build: uvmt_cv32e40p
    description: Hardware performance counter hazard test
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=hpmcounter_hazard_test

  riscv_ebreak_test_0:
    build: uvmt_cv32e40p
    description: Static corev-dv ebreak
    dir: cv32e40p/sim/uvmt
    cmd: make test COREV=YES TEST=riscv_ebreak_test_0

  riscv_arithmetic_basic_test_0:
    build: uvmt_cv32e40p
    description: Static riscv-dv arithmetic test 0
    dir: cv32e40p/sim/uvmt    
    cmd: make test COREV=YES TEST=riscv_arithmetic_basic_test_0
    num: 1

  riscv_arithmetic_basic_test_1:
    build: uvmt_cv32e40p
    description: Static riscv-dv arithmetic test 1
    dir: cv32e40p/sim/uvmt    
    cmd: make test COREV=YES TEST=riscv_arithmetic_basic_test_1
    num: 1

  corev_rand_arithmetic_base_test:
    build: uvmt_cv32e40p
    description: Generated corev-dv arithmetic test
    dir: cv32e40p/sim/uvmt    
    cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_arithmetic_base_test
    num: 200

  corev_rand_instr_test:
    build: uvmt_cv32e40p
    description: Generated corev-dv random instruction test
    dir: cv32e40p/sim/uvmt
    cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_instr_test
    num: 200

  corev_rand_instr_long_stall:
    build: uvmt_cv32e40p
    description: Generated corev-dv random instruction test with long stalls
    dir: cv32e40p/sim/uvmt
    cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_instr_long_stall
    num: 30

  corev_rand_illegal_instr_test:
    build: uvmt_cv32e40p
    description: Generated corev-dv random instruction test with illegal instructions
    dir: cv32e40p/sim/uvmt
    cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_illegal_instr_test
    num: 200

  corev_rand_jump_stress_test:
    build: uvmt_cv32e40p
    description: Generated corev-dv jump stress test
    dir: cv32e40p/sim/uvmt    
    cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_jump_stress_test
    num: 200

  corev_rand_interrupt:
    build: uvmt_cv32e40p
    description: Generated corev-dv random interrupt test
    dir: cv32e40p/sim/uvmt    
    cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt
    num: 200

  corev_rand_debug:
    build: uvmt_cv32e40p
    description: Generated corev-dv random debug test
    dir: cv32e40p/sim/uvmt    
    cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_debug
    num: 50

  corev_rand_debug_single_step:
    build: uvmt_cv32e40p
    description: debug random test with single-stepping
    dir: cv32e40p/sim/uvmt
    cmd: make gen_corev