HDLBits练习答案（持续更新）
HDLBits练习答案
- 1.Getting Started
- 2. Verilog Language
-
- 2.3 Modules:Hierarchy
-
- 2.3.5 Modules and vertors
- 2.3.6 Adder 1
- 2.3.7 Adder 2
- 2.3.8 Carry-select adder
- 2.3.9 Adder-subrtactor
- 2.4 Procedures
-
- 2.4.1 Always block1
- 2.4.2 Always block2
- 2.4.4 If statement
- 2.4.5 If statement latches
- 2.4.6 Case statement--- Always case
- 2.4.6 Priority encoder---Always case2
- 2.4.7 Priority encoder with casez---Always casez
- 2.4.7 Avoid latches---Always nolatches
- 2.5 More Verilog Features
-
- 2.5.1 Conditional ternary operator
- 2.5.2 Reduction operators---Reduction
- 2.5.3 Reduction:Event wider gates---Gates100
- 2.5.4 Combinational for-loop:Vector reversal 2---Vector100r
- 2.5.5 Combinational for-loop:255-bit population count---Popcount255
- 2.5.6 Generate for-loop:100-bit binary adder 2---Adder100i
- 2.5.7 Generate for-loop:100-bit digit BCD adder---Bcdadd100
- 3 Circuits
-
- 3.1 Combinational Logic
-
- 3.1.1 Basic Gates
1.Getting Started
2. Verilog Language
2.3 Modules:Hierarchy
2.3.5 Modules and vertors
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0] q1,q2,q3,qout;
my_dff8 U1(clk, d, q1);
my_dff8 U2(clk, q1, q2);
my_dff8 U3(clk, q2, q3);
always @(*)
begin
case(sel)
2'b00: qout<=d;
2'b01: qout<=q1;
2'b10: qout<=q2;
2'b11: qout<=q3;
endcase
end
assign q=qout;
endmodule
2.3.6 Adder 1
方法1：直接使用变量进行访问，处理方法是将相应的数据按照Module定义的顺序进行调用，参数位置不可以错
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [15:0] suml,sumh;
wire cinl,coutl,couth;
assign cinl=0;
add16 U1(a[15:0], b[15:0], cinl, suml, coutl);
add16 U2(a[31:16], b[31:16], coutl, sumh, couth);
assign sum={
sumh, suml};
endmodule
方法2：使用点变量的方式，好处就是参数位置可以随意调整。
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [15:0] suml,sumh;
wire cinl,coutl,couth;
assign cinl=0;
add16 U1(.b(b[15:0]), .cin(cinl), .sum(suml), .cout(coutl),.a(a[15:0]) );
add16 U2(.a(a[31:16]),.cin(coutl), .sum(sumh), .cout(couth), .b(b[31:16]) );
assign sum={
sumh, suml};
endmodule
2.3.7 Adder 2
此任务是先完成一个小模块add1的设计，两个1bit的数据相加运算，然后再调试add16实现顶层模块的功能
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);//
wire [15:0] suml,sumh;
wire cinl,cinh,coutl,couth;
assign cinl=0