RT-Thread 27. UART设备

1.实现串口通信

这里实现uart0的485通信
MSH命令输入:uart_data_sample,开启线程执行。
输入一段字符串,以’\r’ (0x0D)结尾,回显输入的字符串

2. 代码

//rt_uart.c

#include 
#include 
#include "drv_gpio.h"
#include "delay.h"

#define THREAD_PRIORITY   28
#define THREAD_TIMESLICE  10
#define THREAD_STACK_SIZE    500

#define TP1_PIN   GET_PIN(F, 6)
#define TP2_PIN   GET_PIN(F, 7)
#define TP1_H     rt_pin_write(TP1_PIN, PIN_HIGH)
#define TP1_L     rt_pin_write(TP1_PIN, PIN_LOW)
#define TP2_H     rt_pin_write(TP2_PIN, PIN_HIGH)
#define TP2_L     rt_pin_write(TP2_PIN, PIN_LOW)


#define UART0_CTL_PIN   GET_PIN(A, 7)
#define UART0_CTL_RX()  rt_pin_write(UART0_CTL_PIN, PIN_LOW);delay_us(200);TP1_H
#define UART0_CTL_TX()  TP1_L;rt_pin_write(UART0_CTL_PIN, PIN_HIGH);delay_us(200)


#define SAMPLE_UART_NAME "uart0"
#define DATA_CMD_END '\r' /* 结 束 位 设 置 为 \r, 即 回 车 符 */
#define ONE_DATA_MAXLEN 20 /* 不 定 长 数 据 的 最 大 长 度 */

/* 用 于 接 收 消 息 的 信 号 量 */
static struct rt_semaphore rx_sem;
static rt_device_t serial;
/* 接 收 数 据 回 调 函 数 */
static rt_err_t uart_rx_ind(rt_device_t dev, rt_size_t size)
{
  /* 串 口 接 收 到 数 据 后 产 生 中 断, 调 用 此 回 调 函 数, 然 后 发 送 接 收 信 号 量 */
  if (size > 0)
  {
    rt_sem_release(&rx_sem);
  }
  return RT_EOK;
}

static char uart_sample_get_char(void)
{
  char ch;
  while (rt_device_read(serial, 0, &ch, 1) == 0)
  {
    rt_sem_control(&rx_sem, RT_IPC_CMD_RESET, RT_NULL);
    rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
  }
  return ch;
}

/* 数 据 解 析 线 程 */
static void data_parsing(void)
{
  char ch;
  char data[ONE_DATA_MAXLEN];
  static char i = 0;
  while (1)
  {
    ch = uart_sample_get_char();
    if(ch == DATA_CMD_END)
    {
      data[i++] = '\0';
      rt_kprintf("data=%s\r\n",data);
      UART0_CTL_TX();
      rt_device_write(serial, 0, data,i-1);
      UART0_CTL_RX();
      i = 0;
      continue;
    }
    i = (i >= ONE_DATA_MAXLEN-1) ? ONE_DATA_MAXLEN-1 : i;
    data[i++] = ch;
  }
}

static int uart_data_sample(int argc, char *argv[])
{
  rt_err_t ret = RT_EOK;
  char uart_name[RT_NAME_MAX];
  char str[] = "hello RT-Thread!\r\n";
  
  //TP
  rt_pin_mode(TP1_PIN, PIN_MODE_OUTPUT);
  TP1_H;

  if (argc == 2)
  {
    rt_strncpy(uart_name, argv[1], RT_NAME_MAX);
  }
  else
  {
    rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX);
  }
  UART0_CTL_RX();
  rt_pin_mode(UART0_CTL_PIN, PIN_MODE_OUTPUT);
  /* 查 找 系 统 中 的 串 口 设 备 */
  serial = rt_device_find(uart_name);
  if (!serial)
  {
    rt_kprintf("find %s failed!\n", uart_name);
    return RT_ERROR;
  }
  /* 初 始 化 信 号 量 */
  rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
  /* 以 中 断 接 收 及 轮 询 发 送 模 式 打 开 串 口 设 备 */
  rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
  /* 设 置 接 收 回 调 函 数 */
  rt_device_set_rx_indicate(serial, uart_rx_ind);
  /* 发 送 字 符 串 */
  UART0_CTL_TX();
  rt_device_write(serial, 0, str, (sizeof(str) - 1));
  UART0_CTL_RX();
  /* 创 建 serial 线 程 */
  rt_thread_t thread = rt_thread_create("serial", (void (*)(void *parameter))data_parsing, RT_NULL, THREAD_STACK_SIZE, THREAD_PRIORITY, THREAD_TIMESLICE);
  /* 创 建 成 功 则 启 动 线 程 */
  if (thread != RT_NULL)
  {
    rt_thread_startup(thread);
  }
  else
  {
    ret = RT_ERROR;
  }
  return ret;
}
/* 导 出 到 msh 命 令 列 表 中 */
MSH_CMD_EXPORT(uart_data_sample, uart device sample);

//delay.c

#include "delay.h"
//

static uint32_t fac_us=72;							//us延时倍乘数

//初始化延迟函数
//当使用ucos的时候,此函数会初始化ucos的时钟节拍
//SYSTICK的时钟固定为AHB时钟的1/8
//SYSCLK:系统时钟频率,MHz 
void delay_init(uint8_t SYSCLK)
{
  fac_us=SYSCLK;
}
//延时nus
//nus为要延时的us数.
//注意:nus的值不要大于1000us
void delay_us(uint32_t nus)
{
    uint32_t ticks;
    uint32_t told,tnow,tcnt=0;
    uint32_t reload=SysTick->LOAD;				//LOAD的值
    ticks=nus*fac_us; 						//需要的节拍数
    told=SysTick->VAL;        				//刚进入时的计数器值
    while(1)
    {
        tnow=SysTick->VAL;
        if(tnow!=told)
        {
            if(tnow<told)tcnt+=told-tnow;	//这里注意一下SYSTICK是一个递减的计数器就可以了.
            else tcnt+=reload-tnow+told;
            told=tnow;
            if(tcnt>=ticks)break;			//时间超过/等于要延迟的时间,则退出.
        }
    }
}

#if 1
//延时nms
//nms:要延时的ms数
void delay_ms(uint16_t nms)
{
    uint32_t i;
    for(i=0; i<nms; i++) delay_us(1000);
}
#endif

//delay.h

#ifndef _DELAY_H
#define _DELAY_H

#include "gd32f3x0.h" 

void delay_init(uint8_t SYSCLK);
void delay_ms(uint16_t nms);
void delay_us(uint32_t nus);
#endif

//drv_usart.c

/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author            Notes
 * 2021-06-21     RiceChen          the first version
 */


#include 

#ifdef RT_USING_SERIAL

#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1)
#error "Please define at least one UARTx"
#endif

#include "drv_usart.h"

static struct gd32_usart_config usart_config[] =
{
#ifdef BSP_USING_UART0
    UART0_BUS_CONFIG,
#endif
#ifdef BSP_USING_UART1
    UART1_BUS_CONFIG,
#endif
};

static struct gd32_usart_bus usart_obj[sizeof(usart_config) / sizeof(usart_config[0])];

void gd32_usart_gpio_init(struct gd32_usart_bus *bus)
{
    rcu_periph_clock_enable(bus->config->per_clk);
    rcu_periph_clock_enable(bus->config->tx_gpio_clk);
    rcu_periph_clock_enable(bus->config->rx_gpio_clk);

    gpio_af_set(bus->config->tx_port, bus->config->tx_af, bus->config->tx_pin);
    gpio_af_set(bus->config->rx_port, bus->config->rx_af, bus->config->rx_pin);

    gpio_mode_set(bus->config->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, bus->config->tx_pin);
    gpio_output_options_set(bus->config->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, bus->config->tx_pin);

    gpio_mode_set(bus->config->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, bus->config->rx_pin);
    gpio_output_options_set(bus->config->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, bus->config->rx_pin);

    NVIC_SetPriority(bus->config->irqn, 0);
    NVIC_EnableIRQ(bus->config->irqn);
    usart_deinit(bus->config->periph);
}

rt_err_t gd32_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
    struct gd32_usart_bus *bus = RT_NULL;

    bus = (struct gd32_usart_bus *)serial->parent.user_data;

    gd32_usart_gpio_init(bus);

    usart_baudrate_set(bus->config->periph, cfg->baud_rate);

    switch (cfg->data_bits)
    {
        case DATA_BITS_9:
            usart_word_length_set(bus->config->periph, USART_WL_9BIT);
            break;

        default:
            usart_word_length_set(bus->config->periph, USART_WL_8BIT);
            break;
    }

    switch (cfg->stop_bits)
    {
        case STOP_BITS_2:
            usart_stop_bit_set(bus->config->periph, USART_STB_2BIT);
            break;
        default:
            usart_stop_bit_set(bus->config->periph, USART_STB_1BIT);
            break;
    }

    switch (cfg->parity)
    {
        case PARITY_ODD:
            usart_parity_config(bus->config->periph, USART_PM_ODD);
            break;
        case PARITY_EVEN:
            usart_parity_config(bus->config->periph, USART_PM_EVEN);
            break;
        default:
            usart_parity_config(bus->config->periph, USART_PM_NONE);
            break;
    }

    usart_receive_config(bus->config->periph, USART_RECEIVE_ENABLE);
    usart_transmit_config(bus->config->periph, USART_TRANSMIT_ENABLE);
    usart_enable(bus->config->periph);

    return RT_EOK;
}

rt_err_t gd32_usart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
    struct gd32_usart_bus *bus = RT_NULL;

    bus = (struct gd32_usart_bus *)serial->parent.user_data;

    switch (cmd)
    {
        case RT_DEVICE_CTRL_CLR_INT:
            /* disable rx irq */
            NVIC_DisableIRQ(bus->config->irqn);
            /* disable interrupt */
            usart_interrupt_disable(bus->config->periph, USART_INT_RBNE);

            break;
        case RT_DEVICE_CTRL_SET_INT:
            /* enable rx irq */
            NVIC_EnableIRQ(bus->config->irqn);
            /* enable interrupt */
            usart_interrupt_enable(bus->config->periph, USART_INT_RBNE);
            break;
    }

    return RT_EOK;
}

int gd32_usart_putc(struct rt_serial_device *serial, char c)
{
    struct gd32_usart_bus *bus = RT_NULL;

    bus = (struct gd32_usart_bus *)serial->parent.user_data;

    usart_data_transmit(bus->config->periph, c);
    while((usart_flag_get(bus->config->periph, USART_FLAG_TC) == RESET));

    return 1;
}

int gd32_usart_getc(struct rt_serial_device *serial)
{
    int ch;
    struct gd32_usart_bus *bus = RT_NULL;

    bus = (struct gd32_usart_bus *)serial->parent.user_data;

    ch = -1;
    if (usart_flag_get(bus->config->periph, USART_FLAG_RBNE) != RESET)
        ch = usart_data_receive(bus->config->periph);
    return ch;
}

rt_size_t gd32_usart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
	return RT_EOK;
}

static struct rt_uart_ops usart_ops =
{
    gd32_usart_configure,
    gd32_usart_control,
    gd32_usart_putc,
    gd32_usart_getc,
    gd32_usart_dma_transmit,
};

static void uart_isr(rt_uint32_t periph)
{
    int obj_num = 0;
    struct gd32_usart_bus *bus = RT_NULL;

    obj_num = sizeof(usart_config) / sizeof(usart_config[0]);

    for(int i = 0; i < obj_num; i++)
    {
        if(usart_obj[i].config->periph == periph)
        {
            bus = &usart_obj[i];
            break;
        }
    }

    if(bus != RT_NULL)
    {
         if ((usart_interrupt_flag_get(bus->config->periph, USART_INT_FLAG_RBNE) != RESET) &&
            (usart_flag_get(bus->config->periph, USART_FLAG_RBNE) != RESET))
        {
            rt_hw_serial_isr(&bus->serial, RT_SERIAL_EVENT_RX_IND);
            /* Clear RXNE interrupt flag */
            usart_flag_clear(bus->config->periph, USART_FLAG_RBNE);
        }
    }
}

#ifdef BSP_USING_UART0
void USART0_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();

    uart_isr(USART0);

    /* leave interrupt */
    rt_interrupt_leave();
}
#endif

#ifdef BSP_USING_UART1
void USART1_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();

    uart_isr(USART1);

    /* leave interrupt */
    rt_interrupt_leave();
}
#endif

int rt_hw_usart_init(void)
{
    int obj_num = 0;
    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;

    obj_num = sizeof(usart_config) / sizeof(usart_config[0]);

    for(int i = 0; i < obj_num; i++)
    {
        usart_obj[i].serial.ops = &usart_ops;
        usart_obj[i].serial.config = config;
        usart_obj[i].config = &usart_config[i];

        /* register UART device */
        rt_hw_serial_register(&usart_obj[i].serial,
                              usart_obj[i].config->dev_name,
                              RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                              (void *)&usart_obj[i]);
    }

    return RT_EOK;
}
INIT_BOARD_EXPORT(rt_hw_usart_init);

#endif

//drv_usart.h
//增加tx_af,rx_af

/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author            Notes
 * 2021-06-20     RiceChen          the first version
 */

#ifndef __DRV_USART_H__
#define __DRV_USART_H__

#include 
#include 
#include "gd32f3x0.h"
#include "gd32f3x0_usart.h"
#include "gd32f3x0_exti.h"

struct gd32_usart_config
{
    char *dev_name;
    rt_uint32_t periph;
    IRQn_Type irqn;
    rcu_periph_enum per_clk;
    rcu_periph_enum tx_gpio_clk;
    rcu_periph_enum rx_gpio_clk;
    rt_uint32_t tx_port;
    rt_uint32_t tx_pin;
    rt_uint32_t rx_port;
    rt_uint32_t rx_pin;
    rt_uint32_t tx_af;
    rt_uint32_t rx_af;
};

struct gd32_usart_bus
{
    struct rt_serial_device serial;
    struct gd32_usart_config *config;
};

#ifdef BSP_USING_UART0
#define UART0_BUS_CONFIG                \
    {                                   \
        .dev_name    = "uart0",         \
        .periph      = USART0,          \
        .irqn        = USART0_IRQn,     \
        .per_clk     = RCU_USART0,      \
        .tx_gpio_clk = RCU_GPIOA,       \
        .rx_gpio_clk = RCU_GPIOA,       \
        .tx_port     = GPIOA,           \
        .tx_pin      = GPIO_PIN_9,      \
        .rx_port     = GPIOA,           \
        .rx_pin      = GPIO_PIN_10,     \
        .tx_af       = GPIO_AF_1,       \
        .rx_af       = GPIO_AF_1,       \
    }
#endif /* BSP_USING_UART0 */

#ifdef BSP_USING_UART1
#define UART1_BUS_CONFIG                \
    {                                   \
        .dev_name    = "uart1",         \
        .periph      = USART1,          \
        .irqn        = USART1_IRQn,     \
        .per_clk     = RCU_USART1,      \
        .tx_gpio_clk = RCU_GPIOA,       \
        .rx_gpio_clk = RCU_GPIOA,       \
        .tx_port     = GPIOA,           \
        .tx_pin      = GPIO_PIN_8,      \
        .rx_port     = GPIOA,           \
        .rx_pin      = GPIO_PIN_15,      \
        .tx_af       = GPIO_AF_4,       \
        .rx_af       = GPIO_AF_1,       \
    }
#endif /* BSP_USING_UART1 */

#endif

//drv_gpio.c
//增加GPIOE的存储位置,不然GPIOF会出错

/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author            Notes
 * 2021-06-20     RiceChen          the first version
 */

#include 
#include 

#ifdef RT_USING_PIN

#include "drv_gpio.h"

static const struct pin_index pins[] =
{
    GD32_PIN(1,  A, 0),
    GD32_PIN(2,  A, 1),
    GD32_PIN(3,  A, 2),
    GD32_PIN(4,  A, 3),
    GD32_PIN(5,  A, 4),
    GD32_PIN(6,  A, 5),
    GD32_PIN(7,  A, 6),
    GD32_PIN(8,  A, 7),
    GD32_PIN(9,  A, 8),
    GD32_PIN(10, A, 9),
    GD32_PIN(11, A, 10),
    GD32_PIN(12, A, 11),
    GD32_PIN(13, A, 12),
    GD32_PIN(14, A, 13),
    GD32_PIN(15, A, 14),
    GD32_PIN(16, A, 15),
    GD32_PIN(17, B, 0),
    GD32_PIN(18, B, 1),
    GD32_PIN(19, B, 2),
    GD32_PIN(20, B, 3),
    GD32_PIN(21, B, 4),
    GD32_PIN(22, B, 5),
    GD32_PIN(23, B, 6),
    GD32_PIN(24, B, 7),
    GD32_PIN(25, B, 8),
    GD32_PIN(26, B, 9),
    GD32_PIN(27, B, 10),
    GD32_PIN(28, B, 11),
    GD32_PIN(29, B, 12),
    GD32_PIN(30, B, 13),
    GD32_PIN(31, B, 14),
    GD32_PIN(32, B, 15),
    GD32_PIN(33, C, 0),
    GD32_PIN(34, C, 1),
    GD32_PIN(35, C, 2),
    GD32_PIN(36, C, 3),
    GD32_PIN(37, C, 4),
    GD32_PIN(38, C, 5),
    GD32_PIN(39, C, 6),
    GD32_PIN(40, C, 7),
    GD32_PIN(41, C, 8),
    GD32_PIN(42, C, 9),
    GD32_PIN(43, C, 10),
    GD32_PIN(44, C, 11),
    GD32_PIN(45, C, 12),
    GD32_PIN(46, C, 13),
    GD32_PIN(47, C, 14),
    GD32_PIN(48, C, 15),
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN(51, D, 2),
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,    
    GD32_PIN(65, F, 0),
    GD32_PIN(66, F, 1),
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN(69, F, 4),
    GD32_PIN(70, F, 5),
    GD32_PIN(71, F, 6),
    GD32_PIN(72, F, 7),
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
    GD32_PIN_DEFAULT,
};

static const struct pin_irq_map pin_irq_map[] =
{
    {GPIO_PIN_0,  EXTI0_1_IRQn},
    {GPIO_PIN_1,  EXTI0_1_IRQn},
    {GPIO_PIN_2,  EXTI2_3_IRQn},
    {GPIO_PIN_3,  EXTI2_3_IRQn},
    {GPIO_PIN_4,  EXTI4_15_IRQn},
    {GPIO_PIN_5,  EXTI4_15_IRQn},
    {GPIO_PIN_6,  EXTI4_15_IRQn},
    {GPIO_PIN_7,  EXTI4_15_IRQn},
    {GPIO_PIN_8,  EXTI4_15_IRQn},
    {GPIO_PIN_9,  EXTI4_15_IRQn},
    {GPIO_PIN_10, EXTI4_15_IRQn},
    {GPIO_PIN_11, EXTI4_15_IRQn},
    {GPIO_PIN_12, EXTI4_15_IRQn},
    {GPIO_PIN_13, EXTI4_15_IRQn},
    {GPIO_PIN_14, EXTI4_15_IRQn},
    {GPIO_PIN_15, EXTI4_15_IRQn},
};

struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
    {-1, 0, RT_NULL, RT_NULL},
};

#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
const struct pin_index *get_pin(rt_uint8_t pin)
{
    const struct pin_index *index;

    if (pin < ITEM_NUM(pins))
    {
        index = &pins[pin];
        if (index->index == -1)
        index = RT_NULL;
    }
    else
    {
        index = RT_NULL;
    }

    return index;
};

void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
    const struct pin_index *index = RT_NULL;
    rt_uint32_t pin_mode = 0, pin_pupd = 0, pin_odpp = 0;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return;
    }

    /* GPIO Periph clock enable */
    rcu_periph_clock_enable(index->clk);
    pin_mode = GPIO_MODE_OUTPUT;

    switch(mode)
    {
    case PIN_MODE_OUTPUT:
        /* output setting */
        pin_mode = GPIO_MODE_OUTPUT;
        pin_pupd = GPIO_PUPD_NONE;
        pin_odpp = GPIO_OTYPE_PP;
        break;
    case PIN_MODE_OUTPUT_OD:
        /* output setting: od. */
        pin_mode = GPIO_MODE_OUTPUT;
        pin_pupd = GPIO_PUPD_NONE;
        pin_odpp = GPIO_OTYPE_OD;
        break;
    case PIN_MODE_INPUT:
        /* input setting: not pull. */
        pin_mode = GPIO_MODE_INPUT;
        pin_pupd = GPIO_PUPD_PULLUP | GPIO_PUPD_PULLDOWN;
        break;
    case PIN_MODE_INPUT_PULLUP:
        /* input setting: pull up. */
        pin_mode = GPIO_MODE_INPUT;
        pin_pupd = GPIO_PUPD_PULLUP;
        break;
    case PIN_MODE_INPUT_PULLDOWN:
        /* input setting: pull down. */
        pin_mode = GPIO_MODE_INPUT;
        pin_pupd = GPIO_PUPD_PULLDOWN;
        break;
    default:
            break;
    }

    gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin);
    if(pin_mode == GPIO_MODE_OUTPUT)
    {
        gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_50MHZ, index->pin);
    }
}

void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
    const struct pin_index *index = RT_NULL;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return;
    }

    gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
}

int gd32_pin_read(rt_device_t dev, rt_base_t pin)
{
    int value = PIN_LOW;
    const struct pin_index *index = RT_NULL;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return value;
    }

    value = gpio_input_bit_get(index->gpio_periph, index->pin);
    return value;
}

rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
    rt_uint8_t i;
    for (i = 0; i < 32; i++)
    {
        if ((0x01 << i) == bit)
        {
            return i;
        }
    }
    return -1;
}

rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
{
    rt_int32_t map_index = bit2bitno(pinbit);
    if (map_index < 0 || map_index >= ITEM_NUM(pin_irq_map))
    {
        return RT_NULL;
    }
    return &pin_irq_map[map_index];
};

rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
    const struct pin_index *index = RT_NULL;
    rt_base_t level;
    rt_int32_t hdr_index = -1;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return RT_EINVAL;
    }

    hdr_index = bit2bitno(index->pin);
    if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
    {
        return RT_EINVAL;
    }

    level = rt_hw_interrupt_disable();
    if (pin_irq_hdr_tab[hdr_index].pin == pin &&
        pin_irq_hdr_tab[hdr_index].hdr == hdr &&
        pin_irq_hdr_tab[hdr_index].mode == mode &&
        pin_irq_hdr_tab[hdr_index].args == args)
    {
        rt_hw_interrupt_enable(level);
        return RT_EOK;
    }
    if (pin_irq_hdr_tab[hdr_index].pin != -1)
    {
        rt_hw_interrupt_enable(level);
        return RT_EFULL;
    }
    pin_irq_hdr_tab[hdr_index].pin = pin;
    pin_irq_hdr_tab[hdr_index].hdr = hdr;
    pin_irq_hdr_tab[hdr_index].mode = mode;
    pin_irq_hdr_tab[hdr_index].args = args;
    rt_hw_interrupt_enable(level);

    return RT_EOK;
}

rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
    const struct pin_index *index = RT_NULL;
    rt_base_t level;
    rt_int32_t hdr_index = -1;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return RT_EINVAL;
    }

    hdr_index = bit2bitno(index->pin);
    if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
    {
        return RT_EINVAL;
    }

    level = rt_hw_interrupt_disable();
    if (pin_irq_hdr_tab[hdr_index].pin == -1)
    {
        rt_hw_interrupt_enable(level);
        return RT_EOK;
    }
    pin_irq_hdr_tab[hdr_index].pin = -1;
    pin_irq_hdr_tab[hdr_index].hdr = RT_NULL;
    pin_irq_hdr_tab[hdr_index].mode = 0;
    pin_irq_hdr_tab[hdr_index].args = RT_NULL;
    rt_hw_interrupt_enable(level);

    return RT_EOK;
}

rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
    const struct pin_index *index;
    const struct pin_irq_map *irqmap;
    rt_base_t level;
    rt_int32_t hdr_index = -1;
    exti_trig_type_enum trigger_mode;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return RT_EINVAL;
    }

    if (enabled == PIN_IRQ_ENABLE)
    {
        hdr_index = bit2bitno(index->pin);
        if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
        {
            return RT_EINVAL;
        }

        level = rt_hw_interrupt_disable();
        if (pin_irq_hdr_tab[hdr_index].pin == -1)
        {
            rt_hw_interrupt_enable(level);
            return RT_EINVAL;
        }

        irqmap = &pin_irq_map[hdr_index];

        switch (pin_irq_hdr_tab[hdr_index].mode)
        {
            case PIN_IRQ_MODE_RISING:
                trigger_mode = EXTI_TRIG_RISING;
                break;
            case PIN_IRQ_MODE_FALLING:
                trigger_mode = EXTI_TRIG_FALLING;
                break;
            case PIN_IRQ_MODE_RISING_FALLING:
                trigger_mode = EXTI_TRIG_BOTH;
                break;
            default:
                rt_hw_interrupt_enable(level);
                return RT_EINVAL;
        }

        rcu_periph_clock_enable(RCU_CFGCMP);

        /* enable and set interrupt priority */
        nvic_irq_enable(irqmap->irqno, 5U, 0U);

        /* connect EXTI line to  GPIO pin */
        syscfg_exti_line_config(index->port_src, index->pin_src);

        /* configure EXTI line */
        exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
        exti_interrupt_flag_clear((exti_line_enum)(index->pin));

        rt_hw_interrupt_enable(level);
    }
    else if (enabled == PIN_IRQ_DISABLE)
    {
        irqmap = get_pin_irq_map(index->pin);
        if (irqmap == RT_NULL)
        {
            return RT_EINVAL;
        }
        nvic_irq_disable(irqmap->irqno);
    }
    else
    {
        return RT_EINVAL;
    }

    return RT_EOK;
}

const static struct rt_pin_ops gd32_pin_ops =
{
    gd32_pin_mode,
    gd32_pin_write,
    gd32_pin_read,
    gd32_pin_attach_irq,
    gd32_pin_detach_irq,
    gd32_pin_irq_enable,
    RT_NULL,
};

rt_inline void pin_irq_hdr(int irqno)
{
    if (pin_irq_hdr_tab[irqno].hdr)
    {
        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
    }
}

void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
{
    if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
    {
        pin_irq_hdr(exti_line);
        exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
    }
}

void EXTI0_1_IRQHandler(void)
{
    rt_interrupt_enter();
    GD32_GPIO_EXTI_IRQHandler(0);
    GD32_GPIO_EXTI_IRQHandler(1);
    rt_interrupt_leave();
}

void EXTI2_3_IRQHandler(void)
{
    rt_interrupt_enter();
    GD32_GPIO_EXTI_IRQHandler(2);
    GD32_GPIO_EXTI_IRQHandler(3);
    rt_interrupt_leave();
}

void EXTI4_15_IRQHandler(void)
{
    rt_interrupt_enter();
    GD32_GPIO_EXTI_IRQHandler(4);
    GD32_GPIO_EXTI_IRQHandler(5);
    GD32_GPIO_EXTI_IRQHandler(6);
    GD32_GPIO_EXTI_IRQHandler(7);
    GD32_GPIO_EXTI_IRQHandler(8);
    GD32_GPIO_EXTI_IRQHandler(9);
    GD32_GPIO_EXTI_IRQHandler(10);
    GD32_GPIO_EXTI_IRQHandler(11);
    GD32_GPIO_EXTI_IRQHandler(12);
    GD32_GPIO_EXTI_IRQHandler(13);
    GD32_GPIO_EXTI_IRQHandler(14);
    GD32_GPIO_EXTI_IRQHandler(15);
    rt_interrupt_leave();
}

int rt_hw_pin_init(void)
{
    int result;

    result = rt_device_pin_register("pin", &gd32_pin_ops, RT_NULL);

    return result;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);

#endif

//drv_gpio.h

/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author            Notes
 * 2021-06-20     RiceChen          the first version
 */

#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__

#include "gd32f3x0.h"
#include "gd32f3x0_exti.h"

#define __GD32_PORT(port)  GPIO##port

#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port,      \
                                    GPIO##port, GPIO_PIN_##pin, \
                                    EXTI_SOURCE_GPIO##port,     \
                                    EXTI_SOURCE_PIN##pin}
#define GD32_PIN_DEFAULT            {-1, (rcu_periph_enum)0, 0, 0, 0, 0}

#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN)

struct pin_index
{
    rt_int16_t index;
    rcu_periph_enum clk;
    rt_uint32_t gpio_periph;
    rt_uint32_t pin;
    rt_uint8_t port_src;
    rt_uint8_t pin_src;
};

struct pin_irq_map
{
    rt_uint16_t pinbit;
    IRQn_Type irqno;
};

#endif

//board.c

/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2009-01-05     Bernard      first implementation
 */
#include 
#include 
#include 

#include 
#include 
#include 
#include "delay.h"

/**
  * @brief  This function is executed in case of error occurrence.
  * @param  None
  * @retval None
  */
void Error_Handler(void)
{
    /* USER CODE BEGIN Error_Handler */
    /* User can add his own implementation to report the HAL error return state */
    while (1)
    {
    }
    /* USER CODE END Error_Handler */
}

/** System Clock Configuration
*/
void SystemClock_Config(void)
{
    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
    NVIC_SetPriority(SysTick_IRQn, 0);
}

/**
 * This is the timer interrupt service routine.
 *
 */
void SysTick_Handler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();

    rt_tick_increase();

    /* leave interrupt */
    rt_interrupt_leave();
}

char heap[1024 *16];
/**
 * This function will initial GD32 board.
 */
void rt_hw_board_init()
{
    /* NVIC Configuration */
#define NVIC_VTOR_MASK              0x3FFFFF80
#ifdef  VECT_TAB_RAM
    /* Set the Vector Table base location at 0x10000000 */
    SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
#else  /* VECT_TAB_FLASH  */
    /* Set the Vector Table base location at 0x08000000 */
    SCB->VTOR  = (0x08000000 & NVIC_VTOR_MASK);
#endif

    SystemClock_Config();
  
    delay_init(SystemCoreClock/1000000UL);

#ifdef RT_USING_COMPONENTS_INIT
    rt_components_board_init();
#endif
  
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif

#ifdef BSP_USING_SDRAM
    rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
#else
      rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}

/*@}*/
3.效果

RT-Thread 27. UART设备_第1张图片

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