Verilog刷题笔记13

In this exercise, you will create a circuit with two levels of hierarchy. Your will instantiate two copies of (provided), each of which will instantiate 16 copies of (which you must write). Thus, you must write two modules: and . top_moduleadd16add1top_moduleadd1

Like module_add, you are given a module that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One module computes the lower 16 bits of the addition result, while the second module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored). add16add16add16

Connect the modules together as shown in the diagram below. The provided module has the following declaration: add16add16

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Within each , 16 full adders (module , not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration: add16add1

module add1 ( input a, input b, input cin, output sum, output cout );

Recall that a full adder computes the sum and carry-out of a+b+cin.

In summary, there are three modules in this design:

top_module — Your top-level module that contains two of…
add16, provided — A 16-bit adder module that is composed of 16 of…
add1 — A 1-bit full adder module.

If your submission is missing a , you will get an error message that says . module add1Error (12006): Node instance “user_fadd[0].a1” instantiates undefined entity “add1”
Verilog刷题笔记13_第1张图片
我的解法:

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire [15:0]sum1,sum2;
    wire cout;
	add16 add16_1( 
        .a(a[15:0]), 
        .b(b[15:0]),
        .cin(0), 
        .sum(sum1), 
        .cout(cout) 
    );
	add16 add16_2( 
        .a(a[31:16]), 
        .b(b[31:16]),
        .cin(cout), 
        .sum(sum2), 
        .cout() 
    );  
    assign sum = {sum2,sum1};
endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );

// Full adder module here
    assign {cout , sum} = a + b + cin;
endmodule

结果正确:
Verilog刷题笔记13_第2张图片

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