xilinx FPGA 乘法器ip核（multipler）的使用（VHDL&Vivado）

一、创建除法ip核

 可以选择两个变量数相乘，也可以选择一个变量输入数据和一个常数相乘

可以选择mult（dsp资源）或者lut（fpga资源）

可以选择速度优先或者面积优先

可以自己选择输出位宽

还有时钟使能和复位功能

 二、编写VHDL程序:声明和例化乘法器ip核

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity yunsuan is
PORT (
    CLK : IN STD_LOGIC;
    Nbkg : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    Tobs : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    CE : IN STD_LOGIC
  );
end yunsuan;

architecture Behavioral of yunsuan is

COMPONENT mult_gen_0
  PORT (
    CLK : IN STD_LOGIC;
    A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    CE : IN STD_LOGIC;
    P : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
  );
END COMPONENT;

signal Nbkg_Tobs :  STD_LOGIC_VECTOR(23 DOWNTO 0);

begin

chengf0 : mult_gen_0
  PORT MAP (
    CLK => CLK,
    A => Nbkg,
    B => Tobs,
    CE => CE,
    P => Nbkg_Tobs
  );

end Behavioral;

三、编写仿真程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity yunsuan_tb is

end yunsuan_tb;

architecture Behavioral of yunsuan_tb is
COMPONENT yunsuan
PORT (
    CLK : IN STD_LOGIC;
    Nbkg : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    Tobs : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    CE : IN STD_LOGIC
  );
  END COMPONENT;
    
 --Inputs
   signal clk : std_logic := '0';
   signal  Nbkg :  STD_LOGIC_VECTOR(15 DOWNTO 0);
   signal Tobs :  STD_LOGIC_VECTOR(2 DOWNTO 0);
   signal CE :  STD_LOGIC;

 	--Outputs

   -- Clock period definitions
   constant clk_period : time := 10 ns;
   
begin

 
	-- Instantiate the Unit Under Test (UUT)
   uut: yunsuan PORT MAP (
          clk => clk,
          Nbkg => Nbkg,
          Tobs => Tobs,
          CE => CE
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
     CE <= '0';
     wait for 25ns; 
     CE <= '1';
     Nbkg <= X"1008";
     Tobs <= "100";
     wait for clk_period*1; 
     Nbkg <= X"1018";
     Tobs <= "100";
     wait for clk_period*1; 
     Nbkg <= X"1008";
     Tobs <= "110";
     wait for clk_period*1; 
     Nbkg <= X"1018";
     Tobs <= "101";
     wait for clk_period*1; 
     CE <= '0';
     Nbkg <= X"1008";
     Tobs <= "110";
     wait for clk_period*1; 
     CE <= '1';
     Nbkg <= X"FFFF";
     Tobs <= "100";
     wait for clk_period*1; 
      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;
   
end Behavioral;

四、RTL图：

 五、仿真结果：：可以看到vivado的乘法器ip核和ISE的一样，当ce有效时，乘法器的乘积会在下一个时钟得出。