DSP_TMS320F28335串口通信配置
下面给出28335的串口通信的配置方法， 重点参考串口对应的GPIO的配置、串口控制寄存器的配置、串口中断处理函数的写法。
/*
* configDebug.h
*
* Created on: 2021.08.11
* Author: Heqiunong
*/
#ifndef MYPROGRAM_DEBUG_CONFIGDEBUG_H_
#define MYPROGRAM_DEBUG_CONFIGDEBUG_H_
#include "Debug/getDebug.h"
// Select the Baud rate of SCI
// #define _BAUD_9600_
// #define _BAUD_38400_
// #define _BAUD_115200_
#define _BAUD_460800_
void configDebug(void);
void configScicGpio(void);
void configScicRegister(void);
void ScicInterruptInit(void);
// The communication port for display and control debugging is generally serial port
// SCI, Serial Communications Interface
void configDebug(void)
{
configScicGpio();
configScicRegister();
}
// Configure the multiplexing function of GPIO pin used by Scic
void configScicGpio(void)
{
EALLOW;
GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC)
GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC)
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC)
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 for SCIRXDC operation
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 for SCITXDC operation
EDIS;
}
// Configure relevant registers of Scic
void configScicRegister(void)
{
/*---------------------------------------------SCICCR-------------------------------------------------------------*/
// SCI number of stop bits
ScicRegs.SCICCR.bit.STOPBITS = 0; // 0: One stop bit ▲
// 1: Two stop bit
// SCI parity odd/even selection
ScicRegs.SCICCR.bit.PARITY = 0; // 0: Odd parity
// 1: Even parity
// SCI parity enable
ScicRegs.SCICCR.bit.PARITYENA = 0; // 0: Parity disabled ▲
// 1: Parity is enabled
// Loop Back test mode enable
ScicRegs.SCICCR.bit.LOOPBKENA = 0; // 0: Loop Back test mode disabled
// 1: Loop Back test mode enabled
// SCI multiprocessor mode control bit
ScicRegs.SCICCR.bit.ADDRIDLE_MODE = 0; // 0: Idle-line mode protocol selected
// 1: Address-bit mode protocol selected
// Character-length control bits 2-0
ScicRegs.SCICCR.bit.SCICHAR = 7; // 0: SCICHAR_LENGTH_1 ▲
// 1: SCICHAR_LENGTH_2
// 7: SCICHAR_LENGTH_8
/*---------------------------------------------SCICTL1--------------------------------------------------------------*/
// SCI receive error interrupt enable
ScicRegs.SCICTL1.bit.RXERRINTENA = 0; // 0: Receive error interrupt disabled
// 1: Receive error interrupt enabled
// SCI software reset (active low)
ScicRegs.SCICTL1.bit.SWRESET = 0; // 0: Writing a 0 to this bit initializes the SCI state machines
// and operating flags (registers SCICTL2 and SCIRXST) to the reset condition.
// 1: After a system reset, re-enable the SCI by writing a 1 to this bit.
// SCI transmitter wake-up method select
ScicRegs.SCICTL1.bit.TXWAKE = 0; // 0: Transmit feature is not selected. In idle-line mode: write
// a 1 to TXWAKE, then write data to register SCITXBUF to generate
// an idle period of 11 data bits / In address-bit mode: write a 1 to
// TXWAKE, then write data to SCITXBUF to set the address bit for
// that frame to 1
// SCI sleep.
ScicRegs.SCICTL1.bit.SLEEP = 0; // 0: Sleep mode disabled
// 1: Sleep mode enabled
// SCI Transmitter enable
ScicRegs.SCICTL1.bit.TXENA = 1; // 0: Transmitter disabled ▲
// 1: Transmitter enabled
// SCI receiver enable
ScicRegs.SCICTL1.bit.RXENA = 1; // 0: Prevent received characters from transfer into the ▲
// SCIRXEMU and SCIRXBUF receiver buffers
// 1: Send received characters to SCIRXEMU and SCIRXBUF
/*---------------------------------------------SCICTL2------------------------------------------------------------*/
ScicRegs.SCICTL2.bit.TXINTENA = 1; // SCITXBUF-register interrupt enable ▲
ScicRegs.SCICTL2.bit.RXBKINTENA = 1; // Receiver-buffer/break interrupt enable ▲
/*---------------------------------------------SCIHBAUD & SCILBAUD-------------------------------------------------*/
// BRR = (SCIHBAUD << 8) + (SCILBAUD) = LSPCLK / (SCI Asynchronous Baud * 8) - 1
#ifdef _BAUD_9600_
ScicRegs.SCIHBAUD = 0x0001; // 9600 baud @ LSPCLK = 150/4 = 37.5MHz. ▲
ScicRegs.SCILBAUD = 0x00E7; // 487.28d → 487d
#endif
#ifdef _BAUD_38400_
ScicRegs.SCIHBAUD = 0x0000; // 38400 baud @ LSPCLK = 150/4 = 37.5MHz. ▲
ScicRegs.SCILBAUD = 0x0079; // 121.07d → 121d
#endif
#ifdef _BAUD_115200_
ScicRegs.SCIHBAUD = 0x0000; // 115200 baud @ LSPCLK = 150/4 = 37.5MHz. ▲
ScicRegs.SCILBAUD = 0x0028; // 39.69d → 40d
#endif
#ifdef _BAUD_460800_
ScicRegs.SCIHBAUD = 0x0000; // 460800 baud @ LSPCLK = 150/4 = 37.5MHz. ▲
ScicRegs.SCILBAUD = 0x0009; // 39.69d → 40d
#endif
// Relinquish SCI from Reset 【迷惑行为】
ScicRegs.SCICTL1.all = 0x0023;
/*---------------------------------------------SCIFFTX & SCIFFRX------------------------------------- ------------*/
ScicRegs.SCIFFTX.bit.SCIRST = 1; // SCI Reset
ScicRegs.SCIFFTX.bit.SCIFFENA = 1; // SCI FIFO enable
ScicRegs.SCIFFTX.bit.TXFIFOXRESET = 1; // Transmit FIFO reset
ScicRegs.SCIFFTX.bit.TXFFST = 0; // FIFO status 0: Transmit FIFO is empty
// 1: Transmit FIFO has 1 words
// 10H: Transmit FIFO has 16 words
ScicRegs.SCIFFTX.bit.TXFFINTCLR = 0; // Transmit FIFO clear
ScicRegs.SCIFFTX.bit.TXFFIENA = 0; // Transmit FIFO interrrupt enable
ScicRegs.SCIFFTX.bit.TXFFIL = 14; // TXFFIL4-0 Transmit FIFO interrupt level bits.
ScicRegs.SCIFFRX.bit.RXFFOVRCLR = 1; // RXFFOVF(Receive FIFO overflow) clear
ScicRegs.SCIFFRX.bit.RXFIFORESET = 1; // Receive FIFO reset
ScicRegs.SCIFFRX.bit.RXFFST = 0; // FIFO status 0: Receive FIFO is empty
// 1: Receive FIFO has 1 words
// 10H: Receive FIFO has 16 words
ScicRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Receive FIFO interrupt clear
ScicRegs.SCIFFRX.bit.RXFFIENA = 1; // Receive FIFO interrupt enable
ScicRegs.SCIFFRX.bit.RXFFIL = 14; // Receive FIFO interrupt level bits
}
void ScicInterruptInit(void){
// SCICRXINT INT8.5
// SCICTXINT INT8.6
// SCICRXINT Initial
EALLOW;
PieVectTable.SCIRXINTC = &getScic; // Specify the interrupt service routine
EDIS;
IER |= M_INT8; // Enable CPU Level interrupt
PieCtrlRegs.PIEIER8.bit.INTx5=1; // Enable PIE Level interrupt
// SCICTXINT Initial
// TODO
}
#endif /* MYPROGRAM_DEBUG_CONFIGDEBUG_H_ */
#ifndef MYPROGRAM_DEBUG_GETDEBUG_H_
#define MYPROGRAM_DEBUG_GETDEBUG_H_
#include "variable.h"
#include "main.h"
#include "Drive/switchDrive.h"
#include "Control/configControl.h"
interrupt void getScic(void);
void GetDebugdecode(void);
void getDebugInit(void);
interrupt void getScic(void)
{
for(RxCnt = 0; RxCnt < 14; RxCnt++)
{
RxBuffer[RxCnt] = ScicRegs.SCIRXBUF.all;
if( (RxCnt >= 1) && (RxDeBugStartFlag == 0) ){
if( (RxBuffer[RxCnt-1] == 0xAA) && (RxBuffer[RxCnt]==0x55) ){ // Detect the position of the Header
RxDeBugCnt = 0;
RxDeBugStartFlag = 1;
RxDeBugStartIndex = RxCnt-1; // The Header position
}
}
}
if((RxDeBugStartFlag==1) && (RxIntegrityFlag == 0)){
for(RxCnt = RxDeBugStartIndex; (RxCnt < 14) && (RxIntegrityFlag == 0); RxCnt++){
RxDebugBuffer[RxDeBugCnt] = RxBuffer[RxCnt];
if(RxDeBugCnt==125){
RxDeBugStartFlag = 0;
RxIntegrityFlag = 1;
RxDeBugCnt = 0;
}else{
RxDeBugCnt++;
}
}
RxDeBugStartIndex = 0;
}
if(RxIntegrityFlag==1){
GetDebugdecode();
RxIntegrityFlag = 0;
}
ScicRegs.SCIFFRX.bit.RXFIFORESET = 0; // 0: Write 0 to reset the FIFO pointer to zero, and hold in reset.
ScicRegs.SCIFFRX.bit.RXFIFORESET = 1; // 1: Re-enable receive FIFO operation
ScicRegs.SCIFFRX.bit.RXFFINTCLR = 1; // 1: Write 1 to clear RXFFINT flag in bit 7
PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; // Writing a 1 to the respective interrupt bit clears the bit and enables the PIE block to drive a pulse into
// the CPU interrupt input if an interrupt is pending for that group.
}