risc-v指令集

RISC-V指令集

R TYPE

ADD

ADD rd, rs1, rs2 //x[rd] = x[rs1] + x[rs2]

SUB

SUB rd, rs1, rs2 //x[rd] = x[rs1] - x[rs2]

SLL

SLL rd, rs1, rs2 //x[rd] = x[rs1] << x[rs2]

SLT

SLT rd, rs1, rs2 //x[rd] = signed x[rs1] < x[rs2]

SLTU

SLTU rd, rs1, rs2 //x[rd] = unsigned x[rs1] <  x[rs2]

XOR

XOR rd, rs1, rs2 //x[rd] = x[rs1] ^ x[rs2]

SRL

SRL rd, rs1, rs2 //x[rd] = x[rs1] >> x[rs2]

SRA

SRA rd, rs1, rs2 //x[rd] = x[rs1] >>> x[rs2]

OR

OR rd, rs1, rs2 //x[rd] = x[rs1] | x[rs2]

AND

AND rd, rs1, rs2 //x[rd] = x[rs1] & x[rs2]

I TYPE

ADDI

ADDI rd, rs1, immediate//x[rd] = x[rs1] + x[rs2]

SLTI

SLT rd, rs1, immediate//x[rd] = signed x[rs1] < x[rs2]

SLTIU

SLTIU rd, rs1, immediate//x[rd] = unsigned x[rs1] <  x[rs2]

XORI

XORI rd, rs1, immediate//x[rd] = x[rs1] ^ x[rs2]

ORI

ORI rd, rs1, immediate//x[rd] = x[rs1] | x[rs2]

ANDI

ANDI rd, rs1, immediate//x[rd] = x[rs1] & x[rs2]

SLLI

SLLI rd, rs1, shamt//x[rd] = x[rs1] << shamt

SRLI

SRLI rd, rs1, shamt//x[rd] = x[rs1] >> shamt

SRAI

SRAI rd, rs1, shamt//x[rd] = x[rs1] >>> shamt

I_L TYPE

LB

该指令是从有效地址中读取一个字节(byte)，经符号位扩展后写入rd寄存器。

LB rd，immediate(rs1) //x[rd] = sext ( M [x[rs1] + sext(immediate) ] [31:0] )

LH

该指令是从有效地址中读取两个字节(halfword)，经符号位扩展后写入rd寄存器。

LH rd，immediate(rs1) //x[rd] = sext ( M [x[rs1] + sext(immediate) ] [31:0] )

LW

该指令是从有效地址中读取四个字节(word)，经符号位扩展后写入rd寄存器。

LW rd，immediate(rs1) //x[rd] = sext ( M [x[rs1] + sext(immediate) ] [31:0] )

LBU

该指令是从有效地址中读取一个字节(byte)，经零扩展后写入rd寄存器。

LBU rd，immediate(rs1) //x[rd] = sext ( M [x[rs1] + sext(immediate) ] [31:0] )

LHU

该指令是从有效地址中读取两个字节(halfword)，经零扩展后写入rd寄存器。

LHU rd，immediate(rs1) //x[rd] = sext ( M [x[rs1] + sext(immediate) ] [31:0] )

S TYPE

SB

SB rs2，immediate(rs1) //M [x[rs1] + sext(immediate) ] =x[rs2][7:0]

SH

SH rs2，immediate(rs1) //M [x[rs1] + sext(immediate) ] =x[rs2][15:0]

SW

SW rs2，immediate(rs1) //M [x[rs1] + sext(immediate) ] =x[rs2][31:0]

B TYPE

BEQ

BEQ rs1，rs2，immediate // if (rs1 == rs2)   pc += sext(immediate )

BNE

BNE rs1，rs2，immediate // if (rs1 != rs2)   pc += sext(immediate )

BLT

BLT rs1，rs2，immediate // if (rs1 < rs2)   pc += sext(immediate )

BGE

BGE rs1，rs2，immediate // if (rs1 >= rs2)   pc += sext(immediate )

BLTU

BLTU rs1，rs2，immediate // if (unsigned rs1 

BGEU

BGEU rs1，rs2，immediate // if (unsigned rs1 >= unsigned rs2)   pc += sext(immediate )

J TYPE

JAL

JAL rd, immediate//x[rd] = pc+4; pc += sext(immediate)

JALR

JALR rd, immediate(rs1)//t = pc + 4;  pc = (x[rs1]+sext(immediate)) & 0xffff_fffe;  x[rd]=t 

U TYPE

LUI

LUI rd，immediate //x[rd] = sext(immediate[31:12] << 12)

AUIPC

AUIPC rd，immediate //x[rd] = pc + sext(immediate[31:12] << 12)