Circuits--Sequential Logic--Latches and Flip-Flops--Edgedetect2

网址：https://hdlbits.01xz.net/wiki/Edgedetect2

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);

    reg [7:0]	r_in;
    
    always@(posedge clk)
        begin
            r_in = in;
        end
    always@(posedge clk)
        begin
            anyedge = in ^ r_in;
        end
    
endmodule