广工EDA可逆计数器实验代码（verilog HDL设计代码）

模块代码

// count.v
module Count(Q,C_B,Clr,Clk,updown,D);
    input Clk,updown,Clr;
    input [7:0]D;
    output [7:0]Q;
    output C_B;
    reg [7:0]Q;

    always@(posedge Clk ,posedge Clr)
        if(Clr)
            begin 
                Q = 0;
            end
        else if (Clk&updown)
            begin
            Q = Q + 1;
            end
        else if (Clk&!updown)
            begin
            Q = Q - 1;
            end
        assign C_B = &{updown,Q};
    //assign TC = &{CET, Q};
endmodule

测试代码

// count.v
module Count(Q,C_B,Clr,Clk,updown,D);
    input Clk,updown,Clr;
    input [7:0]D;
    output [7:0]Q;
    output C_B;
    reg [7:0]Q;

    always@(posedge Clk ,posedge Clr)
        if(Clr)
            begin 
                Q = 0;
            end
        else if (Clk&updown)
            begin
            Q = Q + 1;
            end
        else if (Clk&!updown)
            begin
            Q = Q - 1;
            end
        assign C_B = &{updown,Q};
    //assign TC = &{CET, Q};
endmodule