Verilog之同步状态机

1、使用同步时序逻辑设计的必要性


2、状态机的结构
2.1 Mealy状态机与Moore状态机

3、状态机的多种设计方法
同一个状态机的多种设计方式：采用Gray编码的状态机设计，采用独热编码的状态机设计，把输出直接指定为状态码设计 ，两段式状态机设计等。
以如下状态转移图设计状态机为例：
（1）采用Gray编码的状态机设计

module fsm_1(clk,rst_n,A,K1,K2)
input clk,rst_n,A;
output K1,K2;
reg [1:0] state ;
reg K1,K2;

parameter idle = 2'b00, start = 2'b01, stop = 2'b10, clear = 2'b11;

always @(posedge clk)
begin
	if(!rst_n)
		begin
		state <= idle; 
		K1 <= 0;K2 <= 0;
		end
	else 
		begin
			case(state)
				idle:begin 
						if(!rst_n) 
							begin
							state <= idle;
							K1 <= 0;K2 <= 0;
							end
						else if(A)
							begin
							state <= start;
							K1 <=0;
							end
						else state <= state;
					 end
				start:begin
						if(!A) state <= stop;
						else state <= state;
					  end
				stop:begin
						if(!rst_n) 
							begin
							state <= idle;
							K1 <= 0;K2 <= 0;
							end
						else if(A)
							begin
							state <= clear;
							K2 <=1;
							end
					 end
				clear:begin
						if(!rst_n)
							begin
							state <= idle;
							K1 <= 1;K2 <= 0;
							end
						else if(!A)
							begin
							state <= idle;
							K1 <= 1;K2 <= 0;
							end
						else state <= state;
					  end
				default: state <= state;
		end
end

endmodule

（2）采用独热编码的状态机设计

（3）把输出直接指定为状态码设计

module fsm_3(clk,rst_n,A,K1,K2)
input clk,rst_n,A;
output K1,K2;
reg [3:0] state ;
//reg K1,K2;

//parameter idle = 4'b1000, start = 4'b0100, stop = 4'b0010, clear = 4'b0001;

K2_i_j_K1
parameter
  zero  = 4'b0_0_0_0,
  idle  = 4'b0_0_0_1,
  start = 4'b0_1_0_0,
  stop  = 4'b0_0_1_0,
  clear = 4'b1_0_0_0;

always @(posedge clk)
begin
	if(!rst_n)
		state <= zero; 
	else 
			case(state)
				idle,zero:begin 
						if(!rst_n) 
							state <= idle;
						else if(A)
							state <= start;
						else state <= state;
					 end
				start:begin
						if(!A) state <= stop;
						else state <= state;
					  end
				stop:begin
						if(!rst_n) 
							state <= idle;
						else if(A)
							state <= clear;
					 end
				clear:begin
						if(!rst_n)
							state <= idle;
						else if(!A)
							state <= idle;
						else state <= state;
					  end
				default: state <= state;
			endcase
	
end

endmodule

（4）两段式状态机

module fsm_3(clk,rst_n,A,K1,K2)
input clk,rst_n,A;
output K1,K2;
reg [3:0] state ;
reg K1,K2;

parameter idle = 2'b00, start = 2'b01, stop = 2'b10, clear = 2'b11;

always @(posedge clk)
begin
	if(!rst_n)
		state <= idle; 
	else 
			case(state)
				idle:begin 
						if(!rst_n) 
							state <= idle;
						else if(A)
							state <= start;
						else state <= state;
					 end
				start:begin
						if(!A) state <= stop;
						else state <= state;
					  end
				stop:begin
						if(!rst_n) 
							state <= idle;
						else if(A)
							state <= clear;
					 end
				clear:begin
						if(!rst_n)
							state <= idle;
						else if(!A)
							state <= idle;
						else state <= state;
					  end
				default: state <= state;
			endcase
	
end

always @(state or rst_n) //产生K2的组合逻辑
begin
	if(!rst_n)
		K2 = 0;
	else 
		if(state == stop)
			K2 = 1;
		else K2 = 0;
end

always @(state or rst_n) //产生K1的组合逻辑
begin
	if(!rst_n)
		K1 = 0;
	else 
		if(state == clear)
			K1 = 1;
		else K1 = 0;
end

endmodule

4、可综合状态机设计指导原则