串口读写IIC器件 FPGA Verilog HDL

串口读写IIC器件 FPGA Verilog HDL

IIC总线协议实现：

`include "config.v"
module I2C(
    clk,               //system clk 50MHZ
	rstn,              //active low
	data_in,           
   data_out,
	sda,
	scl,
	wr,               //wr=0   write; wr=1  read
	fail,
	req,
	address,
	wr_done,
	rd_done
);


    input clk;
	input rstn;
	input [7:0]data_in;
	input wr;
	input req;
	input [7:0] address;
	
	output [0:0]scl;
	output reg[7:0] data_out;
	
	inout sda;
	output fail;
	output rd_done;
	output wr_done;
	
	reg [7:0] clk_cnt;
	
	wire sda_in;
	reg sda_out;
	
	reg [29:0] state;
	
	reg [0:0]  sda_mode;
	wire clk_en;
	
	parameter IN   =0,
	          OUT  =1;
				 
				 
	parameter         idle      =30'b00_0000_0000_0000_0000_0000_0000_0001,
	                  start     =30'b00_0000_0000_0000_0000_0000_0000_0010,
					  mode0     =30'b00_0000_0000_0000_0000_0000_0000_0100,
					  mode1     =30'b00_0000_0000_0000_0000_0000_0000_100