寄存器Verilog

1。有异步清零端的n位寄存器：

module regn(D,clk,reset,Q);

  parameter n=16;

  input  [n-1] D;

  input  clk,reset;

  output [n-1] reg Q;

 

  always @(negedge reset,posedge clk)

      if(!reset)  //复位端reset低电平有效

         Q<=0;

       else

         Q<=D;

 

endmodule

 

2.D输入端有2选1多路器的D触发器：

module  mux_flipflop(sel,D0,D1,clk,Q);

   input  D0,D1,sel,clk;

   output reg Q;

 

always @(posedge clk)

     if(!sel)

         Q<=D0;

     else

         Q<=D1;

 

endmodule

 

3.四位一位寄存器：

/*当load=1时，让D的值赋给Q；当load=0时，寄存器向右移，right移入最高位Q[3];*/

 

module shift4(D,right,load,clk,Q);

    input  [3:0] D;

    input load ,clk,right;

    output  [3:0]  reg Q;

 

    always @(posedge clk)//注：这里的敏感信号只有一个clk，同步加载；

         if(load==1)

             Q<=D;

         else

         begin

            Q[0]<=Q[1];

            Q[1]<=Q[2];

            Q[2]<=Q[3];

            Q[3]<=right;

         end

 

endmodule

 

4.n位移位寄存器：

module shiftn(D,load,right,clk,Q);           

     parameter  n=16;

     input [n-1] D;

     input load,right,clk;

     output [n-1] reg  Q;

     integer  k;

 

     always  @(posedge clk)

          if(load==1)

               Q<=D;

           else

           begin

               for(k=0;k

                    Q[k]=Q[k+1];

               Q[n-1]=right;

           end

 

endmodule

 

5。四位递增计数器：

/*E为使能计数端，reset为异步复位端。*/

module upcount(D,reset,clk,load,E,Q);

     input [3:0] D;

     input reset,clk,E,load;

     output [3:0] reg Q;

 

     always @(negedge reset,posedge clk)

          if(!reset)

              Q<=0;

          ele if(load)

              Q<=D;

          else  if(E)//注：这里的else是必须的。因为复位端reset优先级最高。

                  Q<=Q+1;

 

endmodule

 

6.递增/减计数器代码：

module updowncounter(D,clk,load,E,updown，Q);

     parameter  n=8;

     input [n-1] D;

     input clk,load,E,updown;

     output [n-1] reg Q;

     integer direction;

 

     always @(clk)

        begin

            direction=-1

            if(reset)

               Q<=0;

             else if(updown)

                direction<=1;

             else if(load)

                 Q<=D;

              else if(E)

                 Q<=Q+direction;

            end

 

endmodule