EDA学习--2选1多路选择器

（一）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY mux21a IS
PORT ( a,b,s :  IN STD_LOGIC ;
    y:OUT  STD_LOGIC);
    END ENTITY mux21a;
    ARCHITECTURE one OF mux21a IS
    BEGIN 
        PROCESS (a,b,s) BEGIN
            IF s='0' THEN y <=a ;
            ELSE y<=b;
            END IF;
        END PROCESS;
    END ARCHITECTURE one;

（二）

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY mux21a IS
 PORT (a,b,s : IN STD_LOGIC;
            y:OUT STD_LOGIC );


END ENTITY mux21a;
ARCHITECTURE one OF mux21a IS
SIGNAL e :STD_LOGIC;
SIGNAL d:STD_LOGIC;
BEGIN 
    d <= a AND (NOT s);
    e <= b AND s;
    y <=d OR e ;
    END ARCHITECTURE one;

（三）

ENTITY mux21a IS
    PORT(
        a:IN BIT;
        b:IN BIT;
        s:IN BIT;
        y:OUT BIT
    );
END ENTITY mux21a;

ARCHITECTURE one OF mux21a IS
        BEGIN
        y<=a WHEN s='0'
        ELSE b;

END ARCHITECTURE one;   

来自：《EDA技术实用教程–VHDL版（第四版）》潘松 黄继业