华为IC测试面试题1

问：输入一个100Mhz的时钟和一个200Mhz的时钟，这两个时钟的相位一致，开始时上升沿对齐，同时拉高。求获得100Mhz移相90°的时钟？
答：下面是verilog代码

module wave_90 (
	input clk_100M,    
	input clk_200M, 
	input rst_n,

	output reg clk_100M_90

);

wire clk_200M_n;
assign clk_200M_n=!clk_200M;
always @(posedge clk_200M_n or negedge rst_n) begin
	if(~rst_n) begin
		 clk_100M_90<= 0;
	end else begin
		 clk_100M_90<=clk_100M ;
	end
end

endmodule

testbench:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: vtf_wave90_test
//////////////////////////////////////////////////////////////////////////////////

module vtf_wave90_test;
// Inputs
reg clk_200M;
reg clk_100M;
reg rst_n;
// Outputs
wire clk_100M_90;

// Instantiate the Unit Under Test (UUT)
wave_90 uut (
	.clk_200M(clk_200M),
    .clk_100M(clk_100M),
    .rst_n(rst_n),
    .clk_100M_90(clk_100M_90)
 );

//Create clock
//always #5 clk_100M =!clk_100M; 
//always #2.5 clk_200M=!clk_200M;
initial fork
	forever begin  #5 clk_100M =!clk_100M;
	end
join

initial begin
	#2.5;
	forever begin  #2.5 clk_200M=!clk_200M;
	end
end

initial 
begin
// Initialize Inputs
    rst_n = 0 ;
    clk_100M=0;
    clk_200M=0;
    #10 rst_n=1 ;
    #10 
    #1000 $finish;
    
end




endmodule

testbench:

从波形可以看出clk_100M_90和clk_100M上升沿相差2.5ns,刚好是偏移了90°相位