processor 第38页

reactos操作系统实现(19)

下面就来了解 CPU 特征识别，如下： /* Get the processor features for the CPU */ FeatureBits =

·2015-11-13 20:51

Multiple address space mapping technique for shared memory wherein a processor operates a fault handling

Virtual addresses from multiple address spaces are translated to real addresses in main memory by generating for each virtual address an address space identifier (AID) identifying its address space. T

·2015-11-13 19:52

给Notepad++ 6.7 加右键菜单带图标

if %processor_archit

·2015-11-13 19:08

Power control within a coherent multi-processing system

Within a multi-processing system including a plurality of processor cores 4, 6operating in accordance

·2015-11-13 18:12

Graphics processing architecture employing a unified shader

The present invention generally relates to graphics processors and, more particularly, to a graphics processor

·2015-11-13 18:49

Operating system coordinated thermal management

A processor's performance state may be adjusted based on processor temperature.

·2015-11-13 18:42

System and method for dynamically adjusting to CPU performance changes

·2015-11-13 18:36

一些重要的计数器

Processor object下的所有计数器 System object下的所有计数器 Memory object下的所有计数器如果客户的程序是.NET程序，还会添加 .

·2015-11-13 18:16

Thermally driven workload scheduling in a heterogeneous multi-processor system on a chip

thermally aware scheduling of workloads in a portable computing device that contains a heterogeneous, multi-processor

·2015-11-13 17:06

PatentTips - Scheduling compute kernel workgroups to heterogeneous processors based on historical processor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to heterogeneous computer systems. 2. Background Art Computers and other such data

·2015-11-13 17:05

PatentTips - Heterogeneous Parallel Primitives Programming Model

the Invention The present invention relates generally to a programming model for a heterogeneous processor

·2015-11-13 17:05

Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode

A processor supports an operating mode in which the default address size is greater than 32 bits and

·2015-11-13 17:24

Multi-core compute cache coherency with a release consistency memory ordering model

A method includes storing, with a first programmable processor, shared variable data to cache lines of

·2015-11-13 16:30

PatentTips - Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes

BACKGROUND OF THE INVENTION This relates to Input/Output (I/O) performance in a host system having multiple processors, and more particularly, to efficient usage of multiple processors in handling I

·2015-11-13 16:36

Virtualizing physical memory in a virtual machine system

A processor including a virtualization system of the processor with a memory virtualization support system

·2015-11-13 16:49

Samza/KafkaAnalysizing

Apache Kafka for messaging, and Apache Hadoop YARN to provide fault tolerance, processor

·2015-11-13 16:27

Virtualizing memory type

A processor, capable of operation in a host machine, including memory management logic to support

·2015-11-13 16:39

Stack switching mechanism in a computer system

A method and mechanism for performing an unconditional stack switch in a processor.

·2015-11-13 15:34

Hypervisor, computer system, and virtual processor scheduling method

A hypervisor calculates the total number of processor cycles (the number of processor cycles

·2015-11-13 15:34

PatentTips - Virtual machine management using processor state information

virtual machine management, and more particularly to efficient scheduling of virtual machines using processor

·2015-11-13 15:47

Interrupt distribution scheme for a computer bus

A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment

·2015-11-13 15:53

Method and apparatus for transitioning between instruction sets in a processor

A data processor (104) is described.

·2015-11-13 15:52

Maintaining processor resources during architectural events

In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address sp

·2015-11-13 14:54

AT&T汇编试讲－－获取CPU Vendor ID

纯汇编代码如下： # a test program to get the processor vendor id # data segment .section .data

·2015-11-13 14:33

Flexible implementation of a system management mode (SMM) in a processor

A system management mode (SMM) of operating a processor includes only a basic set

·2015-11-13 14:59

PatentTips - Compare and exchange operation using sleep-wakeup mechanism

BACKGROUND Typically, a multithreaded processor or a multi-processor system is capable of processing

·2015-11-13 14:57

ARM code for Beginners

Part 1: The ARM Processor Brain Pickard explains how anyone can program in ARM code.

·2015-11-13 13:05

Lock-less buffer management scheme for telecommunication network applications

A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network

·2015-11-13 13:47

System and method for assigning a message

A processor of a plurality of processors includes a processor core and a message manager.

·2015-11-13 13:46

Inter-partition communication in multi-core processor

A multi-core processor includes logical partitions that have respective processor cores, memory areas

·2015-11-13 13:45

Core abstraction layer for telecommunication network applications

sub-system, the core abstraction layer (CAL), is introduced to the middleware layer of the multi-core processor

·2015-11-13 13:43

Lock-less and zero copy messaging scheme for telecommunication network applications

computer-implemented system and method for a lock-less, zero data copy messaging mechanism in a multi-core processor

·2015-11-13 13:42

PatentTips - Increasing turbo mode residency of a processor

BACKGROUND Many modern operating systems (OS's) use the Advanced Configuration and Power Interface (ACPI) standard, e.g., Rev. 3.0b, published Oct. 10, 2006, for optimizing system power. An ACPI imp

·2015-11-13 13:40

PatentTips - Object-oriented processor architecture and operating method

More specifically, the present invention relates to an object-oriented processor architecture and operat

·2015-11-13 13:40

Virtual address cache memory, processor and multiprocessor

An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory con

·2015-11-13 12:21

PatentTips - Optimizing power usage by factoring processor architectural events to PMU

BACKGROUND Processor power consumption has become a major issue in recent years.

·2015-11-13 12:16

DM355 ARM SUBSYSTEM

3.1 DM355 ARM： · ARM926EJ-S - 32-bit RISC processor· 16-KB Instruction cache· 8

·2015-11-13 12:47

Atomic operations on the x86 processors

In the old days when there was a single processor, the operation: ++i;

·2015-11-13 11:52

Adaptively handling remote atomic execution based upon contention prediction

In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically

·2015-11-13 11:52

Method and apparatus for speculative execution of uncontended lock instructions

A method and apparatus for executing lock instructions speculatively in an out-of-order processor are

·2015-11-13 10:33

PatentTips - Zero voltage processor sleep state

BACKGROUND Embodiments of the invention relate to the field of electronic systems and power management. More particularly, embodiments of the invention relate to a method and apparatus for a zero vo

·2015-11-13 10:31

PatentTips - Hamming distance comparison

transmitted in multiple packets, e.g., words, from one element, e.g., cache, to another element, e.g., processor

·2015-11-13 09:09

利用Windows性能计数器(PerformanceCounter)监控

性能对象，就是被监视的对象，典型例子有Processor、Process、Memory、TCP/UDP/IP/ICMP、PhysicalDisk等。

·2015-11-13 08:52

Loadrunner 性能指标定位系统瓶颈

判断CPU瓶颈 1， %processor time 平均值大于95 2， processor queue length大于2 (大于处理器个数+1).可以确定CPU瓶颈 3， CPU

·2015-11-13 07:11

Separate code and data contexts: an architectural approach to virtual text sharing

The present invention provides a processor including a core unit for processing requests from at least

·2015-11-13 07:08

Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction

In response to execution of an acquisition instruction by a first processor amon

·2015-11-13 07:06

性能计数器

性能计数器 LEO服務器CPU使用率 Processor(_Total)\% Processor Time LEO服務器磁盤C讀 PhysicalDisk(0 C:)\Disk

·2015-11-13 07:50

Hadoop自定义Counter

1.通过enum自定义Counter public static num LOG_PROCESSOR_COUNTER { BAD_RECORDS }; 2

·2015-11-13 06:15

数据库服务器计数器

类别计数器名称计数器描述 System Total Processor Time 数据库进程占用的CPU时间。在不同的数据库中以不同的名称表示。

·2015-11-13 05:30

Snoop resynchronization mechanism to preserve read ordering

A processor employing a post-cache (LS2) buffer.

·2015-11-13 05:49

推荐频道

processor