Computer 101

http://computer.howstuffworks.com/question452.htm


Dynamic RAM:

Inside a dynamic RAM (DRAM) chip, each memory cell holds one bit of information and is made up of two parts: a transistor and a capacitor. The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state.

The article then goes onto compare the capacitors on DRAM to buckets, where the DRAM is filled with electrons to store information (storing 1s). These electrons are emptied when information is removed (storing 0s). The problem with capacitors is that they have leaks and lose information quite rapidly. In order to retain the information an outside source (CPU or Memory Controller) has to recharge all of the capacitors holding a 1 before they discharge.
This refresh operation is where dynamic RAM gets its name. Dynamic RAM has to be dynamically refreshed all of the time or it forgets what it is holding. The downside of all of this refreshing is that it takes time and slows down the memory.

Static RAM:

Static RAM uses a completely different technology. In static RAM, a form of flip-flop holds each bit of memory. A flip-flop for a memory cell takes 4 or 6 transistors along with some wiring, but never has to be refreshed. This makes static RAM significantly faster than dynamic RAM. However, because it has more parts, a static memory cell takes a lot more space on a chip than a dynamic memory cell. Therefore you get less memory per chip, and that makes static RAM a lot more expensive. 


Cheaper DRAM is used in main memory while SRAM is commonly used in cache memory



APB（ARM Peripheral BUS)

Kernel通过物理内存地址来管理设备资源（如寄存器等），

IO设备本身使用的是总线地址(bus address)，

• A Data Memory Barrier (DMB) ensures that all explicit memory accesses before the DMB instruction complete before any explicit memory accesses after the DMB instruction start.
  
• A Data Synchronization Barrier (DSB) completes when all instructions before this instruction complete.
• An Instruction Synchronization Barrier (ISB) flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the ISB has been completed.