cocotb questa vcd dumpvars

`timescale 1ns/1ps


module count_up#(parameter COUNTER_WIDTH=4)(clk, reset, count);
input clk; 
input reset; 
output [COUNTER_WIDTH-1:0] count; 
reg [COUNTER_WIDTH-1:0] counter; 

always @(posedge clk)
begin
    if(reset) 
        counter <= 0;
    else 
        counter <= counter + 1; 
end
    
assign count = counter;

// Dump waves
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1, count_up);
  end
endmodule

在vsim 中
vcd2wlf dump.vcd dump.wlf
#然后open dump.wlf

import cocotb
from cocotb.triggers import FallingEdge, Timer
from cocotb.clock import Clock
from cocotb_test.simulator import run
from cocotb.runner import get_runner   #不是#from cocotb_tools.runner import get_runner
import pytest
import os
from pathlib import Path

@cocotb.test()
async def counter_test(dut):
    clock = Clock(dut.clk, 10, units="ns")
    cocotb.start_soon(clock.start())

    dut.reset.value = 1
    await FallingEdge(dut.clk)
    dut.reset.value = 0

    for _ in range(20):
        await FallingEdge(dut.clk)
        print(f"######Count: {dut.count.value}")
        
        #assert 0 <= dut.count.value <= 15, "Count should be between 0 and 15"
        

def test_counter():
    sim = os.getenv("SIM", "questa")  ######
    proj_path = Path(__file__).resolve().parent

    sources = [proj_path / "count_up.v"]

    runner = get_runner(sim)
    runner.build(
        sources=sources,
        hdl_toplevel="count_up",
    )

    runner.test(hdl_toplevel="count_up", test_module="test_bench3,")

# cocotb.runner 例子2
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
import random


import os
from pathlib import Path
from cocotb.runner import get_runner   #不是#from cocotb_tools.runner import get_runner
import sys

# AXI Stream FIFO Testbench
class AXISFIFOTestbench:
    def __init__(self, dut):
        self.dut = dut

        # Create AXI Stream interfaces
        self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst_n)
        self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst_n)

    async def reset(self):
        """Reset the DUT"""
        self.dut.rst_n.value = 0
        await RisingEdge(self.dut.clk)
        await RisingEdge(self.dut.clk)
        self.dut.rst_n.value = 1
        await RisingEdge(self.dut.clk)

    async def run_test(self, num_transactions=10):
        """Run the test"""
        await self.reset()

        # Generate random input data
        input_data_list = []
        for _ in range(num_transactions):
            data = random.randint(0, (1 << 32) - 1)
            tlast = random.randint(0, 1)
            input_data_list.append((data, tlast))
            await self.source.send(data, tlast=tlast)
            self.dut._log.info(f"Generated input data: {data}, tlast: {tlast}")

        # Wait for all outputs to be collected
        output_data_list = []
        while len(output_data_list) < num_transactions:
            output_data = await self.sink.recv()
            output_data_list.append((output_data.tdata, output_data.tlast))
            self.dut._log.info(f"Captured output data: {output_data.tdata}, tlast: {output_data.tlast}")

        # Verify the output
        for i in range(num_transactions):
            input_data, input_tlast = input_data_list[i]
            output_data, output_tlast = output_data_list[i]
            assert input_data == output_data, f"Data mismatch: input={input_data}, output={output_data}"
            assert input_tlast == output_tlast, f"TLAST mismatch: input={input_tlast}, output={output_tlast}"

        self.dut._log.info("Test passed!")

@cocotb.test()
async def test_axis_fifo(dut):
    """Test the AXI Stream FIFO"""
    # Create a clock
    clock = Clock(dut.clk, 10, units="ns")
    cocotb.start_soon(clock.start())

    # Initialize the testbench
    tb = AXISFIFOTestbench(dut)

    # Run the test
    await tb.run_test(num_transactions=20)



def test_axis_fifo_runner():
    """Simulate the adder example using the Python runner.

    This file can be run directly or via pytest discovery.
    """
    hdl_toplevel_lang = os.getenv("HDL_TOPLEVEL_LANG", "verilog")
    #sim = os.getenv("SIM", "icarus")
    sim = os.getenv("SIM", "questa")

    proj_path = Path(__file__).resolve().parent
    print(f"###########proj_path:{proj_path}")
    # equivalent to setting the PYTHONPATH environment variable
    sys.path.append(str(proj_path / "model"))

    if hdl_toplevel_lang == "verilog":
        #sources = [proj_path / "hdl" / "adder.sv"]
        sources = [proj_path / "axis_fifo.sv"]
    else:
        #sources = [proj_path / "hdl" / "adder.vhdl"]
        sources = [proj_path  / "axis_fifo.vhdl"]

    print(f"###########sources:{sources}")
    build_test_args = []
    if hdl_toplevel_lang == "vhdl" and sim == "xcelium":
        build_test_args = ["-v93"]

    # equivalent to setting the PYTHONPATH environment variable
    sys.path.append(str(proj_path / "tests"))

    runner = get_runner(sim)
    runner.build(
        sources=sources,
        hdl_toplevel="axis_fifo",
        always=True,
        build_args=build_test_args,
    )
    runner.test(
        hdl_toplevel="axis_fifo", test_module="test_axis_fifo", test_args=build_test_args
    )


if __name__ == "__main__":
    test_axis_fifo_runner()