Qemu-STM32(十六)：STM32F103加入GPIO控制器

概述

本文主要描述了在Qemu平台中，如何添加STM32F103的GPIO控制器模拟代码。

参考资料

STM32F1XX TRM手册，手册编号：RM0008

添加步骤

1、在hw/arm/Kconfig文件中添加STM32F1XX_GPIO，如下所示:

+号部分为新增加内容

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a956e653..2a66ff5f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -418,6 +418,7 @@ config STM32F103_SOC
     select STM32F1XX_PWR
     select STM32F1XX_FLASH
     select STM32F1XX_USART
+    select STM32F1XX_GPIO

2、在include/hw/arm/stm32f103_soc.h文件中添加

+号部分为新增加内容

diff --git a/include/hw/arm/stm32f103_soc.h b/include/hw/arm/stm32f103_soc.h
index e08171a8..c4c9bc52 100644
--- a/include/hw/arm/stm32f103_soc.h
+++ b/include/hw/arm/stm32f103_soc.h
@@ -28,6 +28,7 @@
 #include "hw/misc/stm32f1xx_pwr.h"
 #include "hw/misc/stm32f1xx_flash.h"
 #include "hw/char/stm32f1xx_usart.h"
+#include "hw/gpio/stm32f1xx_gpio.h"
 
 #define RCC_BASE_ADDR    0x40021000
 #define EXTI_BASE_ADDR   0x40010400
@@ -39,6 +40,15 @@
 #define UART2_BASE_ADDR  0x40004400
 #define UART3_BASE_ADDR  0x40004800
 
+#define STM_NUM_GPIOS       7
+#define STM_GPIO_PORTA      0x40010800
+#define STM_GPIO_PORTB      0x40010c00
+#define STM_GPIO_PORTC      0x40010000
+#define STM_GPIO_PORTD      0x40011400
+#define STM_GPIO_PORTE      0x40011800
+#define STM_GPIO_PORTF      0x40011c00
+#define STM_GPIO_PORTG      0x40012000
+
 #define TYPE_STM32F103_SOC "stm32f103-soc"
 #define STM32F103_SOC(obj) \
     OBJECT_CHECK(STM32F103State, (obj), TYPE_STM32F103_SOC)
@@ -57,6 +67,7 @@ typedef struct STM32F103State {
     STM32F1XXPowerState pwr;
     STM32F1XXFlashState flash;
     STM32F1XXUsartState usart[STM_NUM_USARTS];
+    STM32F1XXGPIOState gpio[STM_NUM_GPIOS];
 
 } STM32F103State;

3、在hw/arm/stm32f103_soc.c文件中添加如下代码片段

+号部分为新增加内容

diff --git a/hw/arm/stm32f103_soc.c b/hw/arm/stm32f103_soc.c
index 09f882da..d673eace 100644
--- a/hw/arm/stm32f103_soc.c
+++ b/hw/arm/stm32f103_soc.c
@@ -36,6 +36,11 @@ static const uint32_t usart_addr[STM_NUM_USARTS] = {
     UART1_BASE_ADDR, UART2_BASE_ADDR, UART3_BASE_ADDR,
 };
 
+static const uint32_t gpio_addr[STM_NUM_GPIOS] = {
+    STM_GPIO_PORTA, STM_GPIO_PORTB, STM_GPIO_PORTC, STM_GPIO_PORTD,
+    STM_GPIO_PORTE, STM_GPIO_PORTF, STM_GPIO_PORTG
+};
+
 static const int usart_irq[STM_NUM_USARTS] = {
     37, 38, 39
 };
@@ -71,6 +76,12 @@ static void stm32f103_soc_initfn(Object *obj)
         object_initialize(&s->usart[i], sizeof(s->usart[i]), TYPE_STM32F1XX_USART);
         qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_GPIOS; i++) {
+        object_initialize(&s->gpio[i], sizeof(s->gpio[i]),
+                          TYPE_STM32F1XX_GPIO);
+        qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f103_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -145,6 +156,17 @@ static void stm32f103_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, usart_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
     }
+    /* GPIO A to G */
+    for (i = 0; i < STM_NUM_GPIOS; i++) {
+        dev = DEVICE(&(s->gpio[i]));
+        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, gpio_addr[i]);
+    }
 }
 

4.在hw/gpio/Kconfig中添加

diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index 1a58f4aa..624110ff 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -8,6 +8,9 @@ config PL061
 config GPIO_KEY
     bool
 
+config STM32F1XX_GPIO
+    bool
+
 config STM32F4XX_GPIO
     bool

5.在hw/gpio/Makefile.objs中添加

diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
index 1b90ae4a..02908b9d 100644
--- a/hw/gpio/Makefile.objs
+++ b/hw/gpio/Makefile.objs
@@ -10,6 +10,7 @@ obj-$(CONFIG_IMX) += imx_gpio.o
 obj-$(CONFIG_RASPI) += bcm2835_gpio.o
 obj-$(CONFIG_NRF51_SOC) += nrf51_gpio.o
 obj-$(CONFIG_ASPEED_SOC) += aspeed_gpio.o
+obj-$(CONFIG_STM32F1XX_GPIO) += stm32f1xx_gpio.o
 obj-$(CONFIG_STM32F4XX_GPIO) += stm32f4xx_gpio.o
 obj-$(CONFIG_STM32H7XX_GPIO) += stm32h7xx_gpio.o
 obj-$(CONFIG_NUC980_GPIO) += nuc980_gpio.o

6.在hw/gpio/创建新文件hw/misc/stm32f1xx_gpio.c

+/*
+ * Copyright (c) 2025 liang yan 
+ *
+ * STM32F1XX GPIO
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see .
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "hw/gpio/stm32f1xx_gpio.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qemu/module.h"
+
+#ifndef STM_GPIO_ERR_DEBUG
+#define STM_GPIO_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (STM_GPIO_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt, __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f1xx_gpio_reset(DeviceState *dev)
+{
+    STM32F1XXGPIOState *s = STM32F1XX_GPIO(dev);
+    s->gpio_crl     = 0x44444444;
+    s->gpio_crh     = 0x44444444;
+    s->gpio_idr     = 0x00000000;
+    s->gpio_odr     = 0x00000000;
+    s->gpio_bsrr    = 0x00000000;
+    s->gpio_brr    = 0x00000000;
+    s->gpio_lckr    = 0x00000000;
+}
+
+static uint64_t stm32f1xx_gpio_read(void *opaque, hwaddr addr,
+                                     unsigned int size)
+{
+    STM32F1XXGPIOState *s = opaque;
+    uint64_t retvalue = 0;
+
+    DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
+    switch(addr) {
+    case STM_GPIO_CRL:
+        retvalue = s->gpio_crl;
+        break;
+    case STM_GPIO_CRH:
+        retvalue = s->gpio_crh;
+        break;
+    case STM_GPIO_IDR:
+        retvalue = s->gpio_idr;
+        break;
+    case STM_GPIO_ODR:
+        retvalue = s->gpio_odr;
+        break;
+    case STM_GPIO_BSRR:
+        retvalue = s->gpio_bsrr;
+        break;
+    case STM_GPIO_BRR:
+        retvalue = s->gpio_brr;
+        break;
+    case STM_GPIO_LCKR:
+        retvalue = s->gpio_lckr;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+            __func__, addr);
+        retvalue = 0;
+        break;
+    }
+    return retvalue;
+}
+
+static void stm32f1xx_gpio_write(void *opaque, hwaddr addr,
+                                uint64_t val64, unsigned int size)
+{
+    STM32F1XXGPIOState *s = opaque;
+    uint32_t value = val64;
+
+    DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);
+    switch(addr) {
+    case STM_GPIO_CRL:
+        s->gpio_crl = value;
+        break;
+    case STM_GPIO_CRH:
+        s->gpio_crh = value;
+        break;
+    case STM_GPIO_IDR:
+        s->gpio_idr = value;
+        break;
+    case STM_GPIO_ODR:
+        s->gpio_odr = value;
+        break;
+    case STM_GPIO_BSRR:
+        s->gpio_bsrr = value;
+        break;
+    case STM_GPIO_BRR:
+        s->gpio_brr = value;
+        break;
+    case STM_GPIO_LCKR:
+        s->gpio_lckr = value;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+            __func__, addr);
+    }
+}
+
+static const MemoryRegionOps stm32f1xx_gpio_ops = {
+    .read = stm32f1xx_gpio_read,
+    .write = stm32f1xx_gpio_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f1xx_gpio = {
+    .name = TYPE_STM32F1XX_GPIO,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(gpio_crl, STM32F1XXGPIOState),
+        VMSTATE_UINT32(gpio_crh, STM32F1XXGPIOState),
+        VMSTATE_UINT32(gpio_idr, STM32F1XXGPIOState),
+        VMSTATE_UINT32(gpio_odr, STM32F1XXGPIOState),
+        VMSTATE_UINT32(gpio_bsrr, STM32F1XXGPIOState),
+        VMSTATE_UINT32(gpio_brr, STM32F1XXGPIOState),
+        VMSTATE_UINT32(gpio_lckr, STM32F1XXGPIOState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void stm32f1xx_gpio_init(Object *obj)
+{
+    STM32F1XXGPIOState *s = STM32F1XX_GPIO(obj);
+
+    memory_region_init_io(&s->mmio, obj, &stm32f1xx_gpio_ops, s,
+                          TYPE_STM32F1XX_GPIO, 0x400);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+}
+
+static void stm32f1xx_gpio_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f1xx_gpio_reset;
+    dc->vmsd = &vmstate_stm32f1xx_gpio;
+}
+
+static const TypeInfo stm32f1xx_gpio_info = {
+    .name          = TYPE_STM32F1XX_GPIO,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F1XXGPIOState),
+    .instance_init = stm32f1xx_gpio_init,
+    .class_init    = stm32f1xx_gpio_class_init,
+};
+
+static void stm32f1xx_gpio_register_types(void)
+{
+    type_register_static(&stm32f1xx_gpio_info);
+}
+
+type_init(stm32f1xx_gpio_register_types)

7.在include/hw/gpio/创建stm32f1xx_gpio.h文件

+/*
+ * Copyright (c) 2025- liang yan 
+ *
+ * STM32F1XX GPIO
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see .
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#ifndef STM32F1XX_GPIO_H
+#define STM32F1XX_GPIO_H
+
+#include "hw/sysbus.h"
+
+#define STM_GPIO_CRL            0x00
+#define STM_GPIO_CRH            0x04
+#define STM_GPIO_IDR            0x08
+#define STM_GPIO_ODR            0x0c
+#define STM_GPIO_BSRR           0x10
+#define STM_GPIO_BRR            0x14
+#define STM_GPIO_LCKR           0x18
+
+#define TYPE_STM32F1XX_GPIO "stm32f1xx-gpio"
+#define STM32F1XX_GPIO(obj) \
+    OBJECT_CHECK(STM32F1XXGPIOState, (obj), TYPE_STM32F1XX_GPIO)
+
+typedef struct {
+    /*  */
+    SysBusDevice parent_obj;
+
+    /*  */
+    MemoryRegion mmio;
+
+    uint32_t gpio_crl;
+    uint32_t gpio_crh;
+    uint32_t gpio_idr;
+    uint32_t gpio_odr;
+    uint32_t gpio_bsrr;
+    uint32_t gpio_brr;
+    uint32_t gpio_lckr;
+
+    qemu_irq irq;
+
+} STM32F1XXGPIOState;
+
+#endif

总结

本文描述了如何在qemu中添加stm32f103平台上GPIO控制器实现步骤。