【verilog】[HDLbits] //Circuits://Sequential Logica://＜Shift Registers＞+＜ more circuts ＞

目录

目录

5-bit LFSR

3-bit LFSR

32-bit LFSR

Shifit register

Shifit register

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Shifit Register

5-bit LFSR

A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

Build this LFSR. The reset should reset the LFSR to 1.

Module Declaration

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);
	reg [4:0] q_next;		// q_next is not a register
	// Convenience: Create a combinational block of logic that computes
	// what the next value should be. For shorter code, I first shift
	// all of the values and then override the two bit positions that have taps.
	// A logic synthesizer creates a circuit that behaves as if the code were
	// executed sequentially, so later assignments override earlier ones.
	// Combinational always block: Use blocking assignments.
	always @(*) begin
		q_next = q[4:1];	// Shift all the bits. This is incorrect for q_next[4] and q_next[2]
		q_next[4] = q[0];	// Give q_next[4] and q_next[2] their correct assignments
		q_next[2] = q[3] ^ q[0];
	end
	
	// This is just a set of DFFs. I chose to compute the connections between the
	// DFFs above in its own combinational always block, but you can combine them if you wish.
	// You'll get the same circuit either way.
	// Edge-triggered always block: Use non-blocking assignments.
	always @(posedge clk) begin
		if (reset)
			q <= 5'h1;
		else
			q <= q_next;
	end
endmodule

 assign  q_next[1:0] = q[2:1];//		assign	q_next = q[4:1];	
    assign  q_next[4] = q[0];    //		assign	q_next[4] = q[0];
    assign q_next[3]=q[4];       //		assign	q_next[2] = q[3] ^ q[0];
    assign q_next[2] = q[3] ^ q[0];//	这样写就不行，会重复赋值

中间那一段 always 的begin里，第一句q_next里就包含了q_next[4]和q_next[2],

因为always语句描述组合逻辑时要用阻塞赋值，逻辑综合器生成电路时，代码是顺序执行的，所以后面的赋值会覆盖前面的赋值。在这儿用非阻塞也能正常运行，但是“Combinational always block: Use blocking assignments.”

用连续赋值也可以

Hint...

The first few states starting at 1 are 00001, 10100, 01010, 00101, ... The LFSR should cycle through 31 states before returning to 00001.