VHDL/Verilog编译错误总结

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Vivado

VHDL

1. [Synth 8-2778] type error near txen_sync ; expected type std_logic_vector
   std_logic类型值不能直接赋值给std_logic_vector
2. [Synth 8-1779] cannot read from ‘out’ object txd ; use ‘buffer’ or ‘inout’
   [Synth 8-1085] txd with mode ‘out’ cannot be read
   输出信号不能直接接ILA ，可以接上一级信号

Verilog

Quartus

VHDL

1. Error(13690): VHDL Type Mismatch error at V3IN1_core.vhd(1376): indexed name returns a value whose type does not match “std_logic_vector”, the type of the target expression
   模块例化时，不能写成 sdi_de => sdiin_vld_4to1(0) ，而是 sdi_de => sdiin_vld_4to1(0 downto 0)

Verilog

Lattice

VHDL

Verilog