HDLbits---Exams/2014 q3c

HDLbits—Exams/2014 q3c
如果不是为了符合题目要求而只是得到答案，那题目很简单

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);

    assign Y0 = ((~y[2]&y[0])|(y==3'b100))&~x | (~y[2]&~y[0])&x;
    assign z = (y == 3'b011) | (y == 3'b100);

endmodule

不过要是使用时钟周期可能就麻烦一点了

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
parameter S0 = 3'd0,S1 = 3'd1,S2 = 3'd2,S3 = 3'd3,S4 = 3'd4;
    reg [2:0] state,next_state;
    always@(posedge clk)begin
        state = next_state;
    end
    
    always@(*)begin
        case(y)
            S0:next_state = x?S1:S0;
            S1:next_state = x?S4:S1;
            S2:next_state = x?S1:S2;
            S3:next_state = x?S2:S1;
            S4:next_state = x?S4:S2;
            default:next_state = S0;
        endcase
    end
    
    always@(*)begin
        case(y)
            S0:begin
                Y0 <= x?1'b1:1'b0;
                z <= 1'b0;
            end
            S1:begin
                Y0 <= x?1'b0:1'b1;
                z <= 1'b0;
            end
            S2:begin
                Y0 <= x?1'b1:1'b0;
                z <= 1'b0;
            end
            S3:begin
                Y0 <= x?1'b0:1'b1;
                z <= 1'b1;
            end
            S4:begin
                Y0 <= x?1'b0:1'b1;
                z <= 1'b1;
            end
            default:begin
                Y0 <= x?1'b0:1'b0;
                z <= 1'b0;
            end
        endcase
    end
endmodule