VHDL之conversion function

 

VHDL Type Cast and Conversion Functions

　　**In ASIC design, do NEVER use integer or natural for signals, use conversion functions instead**

　　The picture below illustrates how to convert between the most common VHDL types.

 

For example:　　

1 signal good_example1    :    std_logic_vector(2 downto 0);

2 signal good_example2    :    std_logic_vector(3 downto 0);

3 

4 good_example1  <=  std_logic_vector(to_unsigned(5, good_example1'length)); 

5 good_example2  <=  std_logic_vector(to_signed(5, good_example2'length)); 

 

numeric_std

1   --===========================================================================

2   -- Numeric array type definitions

3   --===========================================================================

4 

5   type UNSIGNED is array (NATURAL range <> ) of STD_LOGIC;

6   type SIGNED is array (NATURAL range <> ) of STD_LOGIC;