verilog--串并转换

(1)四输入单输出的并串转换模块：

module b_c(clk,rst_n,en,d,q);
input clk,rst_n;
input [3:0]d;
output reg en;
output reg q;

reg [3:0]count;
reg [3:0]data;
always @(posedge clk or negedge rst_n)
begin
    if(rst_n==0)
    begin
       count<=0;
       en<=0;;
       data<=d;
       q<=0;
    end
    else
    begin
       if(count<4)
       begin
           count<=count+1;
           en<=1;
           data<={data[2:0],data[3]};
           q<=data[3];
       end
       else
       begin
       count<=0;
       en<=0;
       q<=0;
       end
    end
end
endmodule

仿真图
(2)单输入四输出的串并转换模块：

module c_b(clk,rst_n,en,d,q);
input clk,rst_n;
input d;
output reg en;
output reg[3:0]q;

reg [3:0]count;
reg [3:0]data;
always @(posedge clk or negedge rst_n)
begin
    if(rst_n==0)
    begin
       count<=0;
       en<=0;;
       data<=4'b0000;
       q<=0;
    end
    else
    begin
       if(count<=4)
       begin
           count<=count+1;
           en<=1;
           data<={data[2:0],d};
           q<=data[3:0];
       end
       else
       begin
       count<=0;
       en<=0;
       q<=0;
       end
    end
end
endmodule

仿真图