AHB总线RAM Verilog实例

  1 //***************************************************************************
  2 //   Copyright(c)2017, Lyu Yang
  3 //   All rights reserved
  4 //
  5 //   File name        :   ahb_ram.v
  6 //   Module name      :   
  7 //   Author           :   Lyu Yang
  8 //   Email            :   
  9 //   Date             :   2016-12-00
 10 //   Version          :   v1.0
 11 //
 12 //   Abstract         :
 13 //
 14 //   Modification history
 15 //   ------------------------------------------------------------------------
 16 // Version       Date(yyyy/mm/dd)   name
 17 // Description
 18 //
 19 // $Log$
 20 //***************************************************************************
 21 `timescale 1ns / 100ps
 22 module apb_ram #(
 23     parameter   AW = 10,
 24                 DW = 32
 25 )(
 26 // --------------------------------------------------------------------------
 27 // Port Definitions
 28 // --------------------------------------------------------------------------
 29     input  wire                     HCLK,      // Clock
 30     input  wire                     HRESETn,   // Reset
 31 
 32     input  wire                     HSEL,      // Device select
 33     input  wire           [AW-1:0]  HADDR,     // Address
 34     input  wire           [1:0]     HTRANS,    // Transfer control
 35     input  wire           [2:0]     HSIZE,     // Transfer size
 36     input  wire           [3:0]     HPROT,     // Protection control
 37     input  wire                     HWRITE,    // Write control
 38     input  wire                     HREADY,    // Transfer phase done
 39     input  wire        [DW-1:0]     HWDATA,    // Write data
 40 
 41     output wire                     HREADYOUT, // Device ready
 42     output reg         [DW-1:0]     HRDATA,    // Read data output
 43     output wire                     HRESP      // Device response
 44 );
 45 
 46 // Byte Align
 47 localparam  BYTE_BITS   = 8,
 48             OFST_BITS   = 2,
 49             WORD_NUM    = 2**(AW-OFST_BITS);
 50 
 51 // Memory Registers
 52 reg    [DW-1:0]    mem[0:WORD_NUM-1];
 53 
 54 // synthesis translate_off
 55 initial begin
 56     $readmemh("../software/data.txt", mem);
 57 end
 58 // synthesis translate_on
 59 
 60 reg        [AW-1:OFST_BITS]    wr_adr;
 61 wire    [AW-1:OFST_BITS]    ram_adr;
 62 
 63 reg        ram_wr, ram_rd;
 64 
 65 always @(posedge HCLK or negedge HRESETn)
 66 begin
 67     if (!HRESETn)
 68         wr_adr <= 'd0;
 69     else if (HSEL && HREADY)
 70         wr_adr <= HADDR[AW-1:OFST_BITS];
 71 end
 72 
 73 assign ram_adr = ram_wr ? wr_adr : HADDR[AW-1:OFST_BITS];
 74 
 75 always @(posedge HCLK or negedge HRESETn)
 76 begin
 77     if (!HRESETn)
 78         ram_wr <= 1'b0;
 79     else begin
 80         if (HSEL && (HTRANS[1] == 1'b1) && HWRITE)
 81             ram_wr <= 1'b1;
 82         else
 83             ram_wr <= 1'b0;
 84     end
 85 end
 86 
 87 always @(*)
 88 begin
 89     if (HSEL && (HTRANS[1] == 1'b1) && !HWRITE)
 90         ram_rd = 1'b1;
 91     else
 92         ram_rd = 1'b0;
 93 end
 94 
 95 always @(posedge HCLK or negedge HRESETn)
 96 begin
 97     if (!HRESETn)
 98         HRDATA <= 'd0;
 99     else begin
100         if (ram_wr)
101             mem[ram_adr]  <= HWDATA;
102         else if (ram_rd)
103             HRDATA <= mem[ram_adr];
104         else
105             HRDATA <= 'd0;
106     end
107 end
108 
109 assign HREADYOUT = 1'b1;
110 assign HRESP     = 1'b0;
111 
112 endmodule

 

转载于:https://www.cnblogs.com/lyuyangly/p/4852710.html