VHDL——APB总线读写操作procedure

概述

用于simulation的APB总线读写操作procedure，袁神指导，哈哈

APB写操作

procedure apbwrite  ( 
                      signal psel : out std_logic;
                      signal penable,pwrite : out std_logic;
                      signal paddr : out std_logic_vector(31 downto 0);
                      signal pwdata : out std_logic_vector(31 downto 0);
                       addrval : in std_logic_vector(31 downto 0);
                       dataval : in std_logic_vector(31 downto 0)
                    ) is 
begin
--T0
  paddr <= (others => '0');
  pwrite <= '0';
  psel <= '0'; 
  penable <= '0';
  pwdata <= (others => '0');
  wait for 20 ns;
--T1
  paddr <= addrval;
  pwrite <= '1';
  psel <= '1'; 
  penable <= '0';
  pwdata <= dataval;
  wait for 20 ns;

--T2
  penable <= '1';
  wait for 20 ns;
--T3
  psel <= '0'; 
  penable <= '0';
  wait for 20 ns ;
--T4
  paddr <= (others => '0');
  pwrite <= '0';
  psel <= '0'; 
  penable <= '0';
  pwdata <= (others => '0');
  wait for 20 ns;
end procedure;

APB读操作

procedure apbread  (  
                      signal psel : out std_logic;
                      signal penable,pwrite : out std_logic;
                      signal paddr : out std_logic_vector(31 downto 0);
                      signal prdata : in std_logic_vector(31 downto 0);
                      constant addrval : in std_logic_vector(31 downto 0);
                      signal dataval : out std_logic_vector(31 downto 0)
                    ) is
begin
--T0
  paddr <= (others => '0');
  pwrite <= '0';
  psel <= '0'; 
  penable <= '0';
  --pwdata <= (others => '0');
  wait for 20 ns;
--T1
  paddr <= addrval;
  pwrite <= '0';
  psel <= '1'; 
  --pwdata <= (others => '0');
  wait for 20 ns;
--T2
  penable <= '1';
  dataval<= prdata;
  wait for 20 ns;

--T3
  psel <='0';
  penable <= '0';
  wait for 20 ns;
--T4 
  paddr <= (others => '0');
  pwrite <= '0';
  psel <= '0'; 
  penable <= '0';
  --pwdata <= (others => '0');
  wait for 20 ns;

end procedure;